Um.. wow. DDR-333 on that bus means 10.6 GBps!!! That kind of bandwidth in the consumer sector is only seen on ultra high end graphics cards, such as the GeForce 4 Ti 4600. This kind of bandwidth, coupled with PowerPC's efficient memory architecture would create some serious competition for the PC.
That DDR400 must be overclocked DDR333 memory... Kinda like PC150 is just overclocked PC133 memory. IIRC, Micron & the rest of the DDR developers have stated that DDR333 was going to be the end of the line before moving to DDRII.
Besides, DDR333 hasn't been out (at least not in a reliable form) for more than a few months... Given that there's damn near a year between release of new memory standards, it seems odd to see DDR400 so soon.
The problem with real PC400 in a DIMM package is that you can only reliably have 2 banks of memory (1 DIMM) working on the motherboard. A computer with only one DIMM is kind of limited as a professional workstation.
<strong>Um.. wow. DDR-333 on that bus means 10.6 GBps!!! That kind of bandwidth in the consumer sector is only seen on ultra high end graphics cards, such as the GeForce 4 Ti 4600. This kind of bandwidth, coupled with PowerPC's efficient memory architecture would create some serious competition for the PC.
Hope it's true!</strong><hr></blockquote>
This thread has gotten pretty long, and I'm not sure which bus you are refering to. Certainly none of the ones discussed approach 10 GBytes/sec, and most exceed 10 Gbits/sec. The RapidIO bus discussed will be in the 2-4 GBytes/sec range. HyperTransport can theoretically reach 12 GBytes/sec, so that could be it... but the speed of the bus doesn't change the speed of DDR333 memory. A 64-bit wide DDR333 implementation will have a throughput of roughly 2.5 GBytes/sec. A 128-bit implementation could double that to rougly 5 GBytes/sec. I'd be surprised to see anything wider (pleasantly surprised, mind you). These are very good speeds.
There is no DDR400 spec, and DDR333 is rare enough that I don't expect to see it in an Apple machine. DDR266 is what I'm hoping to see, which ought to deliver about 2 GBytes/sec (or close to it). DDR-II is still a ways off yet. I suppose there is an outside chance Apple could use RAMBus, but I wouldn't be too happy about that... although it would be fast.
The nice thing about the new busses discussed here is that they are faster than the available memory, which means there is some room for growth.
Well the new macs will probably have 333 DDR because apple would have learned from it mistakes (with some luck ) and taken some action that the macs are at least on a par with future PCs. This is because apple is targetting professional markets where PCs are far more technically advanced.
<strong>Well the new macs will probably have 333 DDR because apple would have learned from it mistakes (with some luck ) and taken some action that the macs are at least on a par with future PCs. This is because apple is targetting professional markets where PCs are far more technically advanced.</strong><hr></blockquote>
Heh, you're optimistic. Actually there are good reasons why Apple might stop short of a DDR333 implementation. Its more expensive, less common, and there have been some technical problems with PC's using it. The performance gain over DDR266 is only about 25% (and if the 100% gain of DDR266 over SDRAM only turns into 10-15% in the benchmarks, then it'll be a realized improvement of only 2.5-3%) then it may not be worth it for Apple to pay the price and take the risks. It would be a better idea to spend the extra money to increase the base RAM configuration so that MacOSX runs faster.
This thread has gotten pretty long, and I'm not sure which bus you are refering to. Certainly none of the ones discussed approach 10 GBytes/sec, and most exceed 10 Gbits/sec. The RapidIO bus discussed will be in the 2-4 GBytes/sec range. HyperTransport can theoretically reach 12 GBytes/sec, so that could be it... but the speed of the bus doesn't change the speed of DDR333 memory. A 64-bit wide DDR333 implementation will have a throughput of roughly 2.5 GBytes/sec. A 128-bit implementation could double that to rougly 5 GBytes/sec. I'd be surprised to see anything wider (pleasantly surprised, mind you). These are very good speeds.
</strong><hr></blockquote>
Well, I sort of extrapolated the system for calculating bandwidth from graphics cards articles I've seen. That is, the hertz rating times sixteen. I'm sure you know it better than I .
Well, I sort of extrapolated the system for calculating bandwidth from graphics cards articles I've seen. That is, the hertz rating times sixteen. I'm sure you know it better than I .
It must be gigabits per second, I suppose.</strong><hr></blockquote>
No gigabytes is correct... here's why:
The x16 is because many graphics boards use a 128-bit bus. Some of them may even be using 256-bit buses... although the memory and bus usually have a fairly radical organization, which is possible due to the nature of graphics (which by its nature is very highly parallel and very deeply pipelined). The memory is also tightly coupled to the graphics chip & not expandable. Think of it as 4 x 64-bit busses, rather than one 256-bit bus. The latest nVidia highest end graphics cards manage a little over 10 GBytes/sec (as you mentioned) by using this mechanism.
This kind of configuration doesn't really work for the main CPU, although with the advent of onchip memory controllers and per-CPU memory some of this will move to the motherboard. If Dorsal's description of the system is accurate then a dual G5 machine, could be built each with its own 128-bit bus to its own private memory, would effectively have a 2 x 128-bit memory bus. If the memory is kept very close to the processor(s) then it might be possible that the bus can be wider and/or faster than 128-bit 133 MHz double pumped, but I won't speculate on that.
Adding more processors effectively widens the bus from a system viewpoint, although not from a single processor's viewpoint. This organization has a significant impact on the operating system, however, and it will be interesting to see how MacOSX deals with that. Processor's accessing eachother's memory would see a severe speed penalty -- on both processors. This would mean that either processes need to be bound to processors (limiting), and/or a sophisticated paging method for transfering whole virtual memory pages between processors is required... doing it at the cache level would involve a great deal of overhead.
It Dorsal is accurate and Apple gets the OS right, these machines will be very fast -- especially in multiprocessor configurations.
I should also add that they could also build these machines with two processors on the same daughtercard, sharing the same memory. This is probably more likely, but without knowing more about the on-chip memory controller its hard to say how it would work.
As long as the G5s are fast, compared to PCs, then nothing else matters, because that is the main reason apple isn't doing well in some professional markets.
<strong>As long as the G5s are fast, compared to PCs, then nothing else matters, because that is the main reason apple isn't doing well in some professional markets.</strong><hr></blockquote>
<strong>As long as the G5s are fast, compared to PCs, then nothing else matters, because that is the main reason apple isn't doing well in some professional markets.</strong><hr></blockquote>
Is there any actual evidence (e.g. user surveys) for this oft-repeated assertion?
I think the main difference is from having 500Mhz DDR as a cache, and having it as mia memory is that the memory at that speed is not reliable enough to be used in large amounts.
Someone correct me if I'm wrong, but it is only the very basics I understand. <img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />
It's not so much the amount as it is the trace distances on the motherboard. Also RAM going through a DIMM slot will limit the speed. That's one reason why Graphics RAM is generally faster than main RAM.
[quote]If there is no such thing as DDR 400MHZ, could someone tell me what the 500MHZ DDR L3 Cache in the Dual Tower is. I really don't know <hr></blockquote>
The cache is SRAM, main memory would be DDR SDRAM. Different memory design, basically. (SRAM is much, MUCH more expensive than DDR SDRAM...)
"Considering that PowerMac sales are half what they were in 1999, it is a valid assertion."
No actually it's not a valid assertion, considering all PC sales have been hit incredibly hard since 1999. Since then there's been an industry-wide slowdown as everyone knows. It isn't limited to PowerMacs, or due to the fact that some think they are underpowered.
Comments
Hope it's true!
Besides, DDR333 hasn't been out (at least not in a reliable form) for more than a few months... Given that there's damn near a year between release of new memory standards, it seems odd to see DDR400 so soon.
<strong>Um.. wow. DDR-333 on that bus means 10.6 GBps!!! That kind of bandwidth in the consumer sector is only seen on ultra high end graphics cards, such as the GeForce 4 Ti 4600. This kind of bandwidth, coupled with PowerPC's efficient memory architecture would create some serious competition for the PC.
Hope it's true!</strong><hr></blockquote>
This thread has gotten pretty long, and I'm not sure which bus you are refering to. Certainly none of the ones discussed approach 10 GBytes/sec, and most exceed 10 Gbits/sec. The RapidIO bus discussed will be in the 2-4 GBytes/sec range. HyperTransport can theoretically reach 12 GBytes/sec, so that could be it... but the speed of the bus doesn't change the speed of DDR333 memory. A 64-bit wide DDR333 implementation will have a throughput of roughly 2.5 GBytes/sec. A 128-bit implementation could double that to rougly 5 GBytes/sec. I'd be surprised to see anything wider (pleasantly surprised, mind you). These are very good speeds.
There is no DDR400 spec, and DDR333 is rare enough that I don't expect to see it in an Apple machine. DDR266 is what I'm hoping to see, which ought to deliver about 2 GBytes/sec (or close to it). DDR-II is still a ways off yet. I suppose there is an outside chance Apple could use RAMBus, but I wouldn't be too happy about that... although it would be fast.
The nice thing about the new busses discussed here is that they are faster than the available memory, which means there is some room for growth.
[ 04-06-2002: Message edited by: Programmer ]</p>
<strong>Well the new macs will probably have 333 DDR because apple would have learned from it mistakes (with some luck
Heh, you're optimistic.
<strong>
This thread has gotten pretty long, and I'm not sure which bus you are refering to. Certainly none of the ones discussed approach 10 GBytes/sec, and most exceed 10 Gbits/sec. The RapidIO bus discussed will be in the 2-4 GBytes/sec range. HyperTransport can theoretically reach 12 GBytes/sec, so that could be it... but the speed of the bus doesn't change the speed of DDR333 memory. A 64-bit wide DDR333 implementation will have a throughput of roughly 2.5 GBytes/sec. A 128-bit implementation could double that to rougly 5 GBytes/sec. I'd be surprised to see anything wider (pleasantly surprised, mind you). These are very good speeds.
</strong><hr></blockquote>
Well, I sort of extrapolated the system for calculating bandwidth from graphics cards articles I've seen. That is, the hertz rating times sixteen. I'm sure you know it better than I
It must be gigabits per second, I suppose.
<strong>
Well, I sort of extrapolated the system for calculating bandwidth from graphics cards articles I've seen. That is, the hertz rating times sixteen. I'm sure you know it better than I
It must be gigabits per second, I suppose.</strong><hr></blockquote>
No gigabytes is correct... here's why:
The x16 is because many graphics boards use a 128-bit bus. Some of them may even be using 256-bit buses... although the memory and bus usually have a fairly radical organization, which is possible due to the nature of graphics (which by its nature is very highly parallel and very deeply pipelined). The memory is also tightly coupled to the graphics chip & not expandable. Think of it as 4 x 64-bit busses, rather than one 256-bit bus. The latest nVidia highest end graphics cards manage a little over 10 GBytes/sec (as you mentioned) by using this mechanism.
This kind of configuration doesn't really work for the main CPU, although with the advent of onchip memory controllers and per-CPU memory some of this will move to the motherboard. If Dorsal's description of the system is accurate then a dual G5 machine, could be built each with its own 128-bit bus to its own private memory, would effectively have a 2 x 128-bit memory bus. If the memory is kept very close to the processor(s) then it might be possible that the bus can be wider and/or faster than 128-bit 133 MHz double pumped, but I won't speculate on that.
Adding more processors effectively widens the bus from a system viewpoint, although not from a single processor's viewpoint. This organization has a significant impact on the operating system, however, and it will be interesting to see how MacOSX deals with that. Processor's accessing eachother's memory would see a severe speed penalty -- on both processors. This would mean that either processes need to be bound to processors (limiting), and/or a sophisticated paging method for transfering whole virtual memory pages between processors is required... doing it at the cache level would involve a great deal of overhead.
It Dorsal is accurate and Apple gets the OS right, these machines will be very fast -- especially in multiprocessor configurations.
I should also add that they could also build these machines with two processors on the same daughtercard, sharing the same memory. This is probably more likely, but without knowing more about the on-chip memory controller its hard to say how it would work.
[ 04-07-2002: Message edited by: Programmer ]</p>
<strong>As long as the G5s are fast, compared to PCs, then nothing else matters, because that is the main reason apple isn't doing well in some professional markets.</strong><hr></blockquote>
No computer company is doing well at this time.
<strong>As long as the G5s are fast, compared to PCs, then nothing else matters, because that is the main reason apple isn't doing well in some professional markets.</strong><hr></blockquote>
Is there any actual evidence (e.g. user surveys) for this oft-repeated assertion?
<strong>
Is there any actual evidence (e.g. user surveys) for this oft-repeated assertion?</strong><hr></blockquote>
Considering that PowerMac sales are half what they were in 1999, it is a valid assertion.
Someone correct me if I'm wrong, but it is only the very basics I understand. <img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />
The cache is SRAM, main memory would be DDR SDRAM. Different memory design, basically. (SRAM is much, MUCH more expensive than DDR SDRAM...)
<strong>Well the new macs will probably have 333 DDR because apple would have learned from it mistakes </strong><hr></blockquote>
I hope Apple has really learned from it's mistakes and will never again use memory that's not common in the market!
"Considering that PowerMac sales are half what they were in 1999, it is a valid assertion."
No actually it's not a valid assertion, considering all PC sales have been hit incredibly hard since 1999. Since then there's been an industry-wide slowdown as everyone knows. It isn't limited to PowerMacs, or due to the fact that some think they are underpowered.