Sort of like the rumors last year of G5s at 1.2, 1.4, and 1.6 GHz. A clever ruse played on the internet Mac community. Someone will get a great laugh out of this new 8500 rumor.
<strong>I think this thread has pretty much stayed on topic and is very informative....
anyway...
I just came into some information on the GPUL I am still digesting. Sometimes some juicy info can come by... But L2 cache is 512KB 8-way set associative connected by a wide bus. L1 is fully inclusive and is 32KB for data and 64KB for instruction. It is held in the L2 also.
I will try and make sense of other info.</strong><hr></blockquote>
The information is either correct or comes from sources like this:
It is a technical article from IBM discussing the Power4 on which the GPUL is based. It sounds like the GPUL will be one core and one of three L2 caches from the Power4. The amount of data and instruction L1 caches are the same in this article as the above rumor.
I have yet to see someone give an authoritative answer to the question of who has the rights to Altivec. People here keep restating as fact that IBM can freely use it or as fact that Motorola holds the exclusive rights. Can someone show me something that says exactly which is the case? I wonder if it is something in between. IBM can use the instructions but not the silicon layout. I.E. they have to design their own version of the instructions. (Although it would seem easier to just pay Motorola than to do that.)
If they had complete rights, it would seem that the GPUL would be a matter of marrying a single Power4 core to an Altivec unit. That would certainly be a lot less work than recreating the whole thing. It would also point to a quicker release date.
Could it be that Apple is holding up all of their Hardware updates, so they can introduce a whole new line of processors (because the performance gap would be too great between iMac-Powermac,ibook-powerboook), also with new mobo's?
Fact: iMac gets new display but no speed bump.
PowerMac gets minor speedbump to keepselling until Jan-march, with promotion.
Ibook and powerbook is pretty quite the last 6 months about them.
IBM is scheduled to discuss its 64-bit PowerPC chip, which has drawn a lot of attention from the Macintosh and Linux communities. Since the PowerPC chip uses a different instruction set than chips used with Microsoft's Windows technology, it can't be used in Windows PCs. It is expected to begin its life in low-end servers, and will also appear in workstations over time, but is "the natural upgrade path for the Apple community," said Kevin Krewell, senior editor of the Microprocessor Report in San Jose.
"(The PowerPC) is the answer to the Macintosh question of 'Where do we go from here?' " Krewell said. The processor will ship in the second half of 2003, he said. An IBM spokesman would not confirm the shipping date, citing the company's policy of not discussing unannounced information.
Chipsets have ALWAYS been evolutionary. You just can't start from scratch with something completely new. With the U2 (UniNorth IS gone, U2 is the successor) controller, we have dual ATA-100 and DDR RAM controllers. With UniNorth 7 (from memory) we had gigabit ethernet. The first g4 uninorth saw the introduction of AGP. It's always going to be gradual. The GPUL chipset will probably be like the current one but with ApplePI and maybe one or two new features.
Barto</strong><hr></blockquote>
Not true. ApplePi is a point to point switched bus from the information that was shared with me. That means at such high speeds only one device will be able to be connected to the processor via ApplePi. ApplePi runs at a 2:1 ration from the processor core speed. That means at 1.6GHz you have a bus that runs at 800MHz, 1.8GHz and it runs at 900MHz. At these speeds it suggests ApplePi has a narrow bus width (16-32bit, my money is at 16bit) and it is based on a known standard like HyperTransport or RapidIO. Unlike MPX you will have only one direct connection to a device.
The information I got also made strong suggestions that the memory controller was NOT on die like previously suggested but the processor has a memory controller interface to connect to an external memory controller. This is good because finally the bus has enough bandwidth to supply the processor with memory bandwidth and it gives the system maker the freedom to use whatever memory technology they wish (DDR, DDR-II, RAMbus, etc.). POWER4 systems use proprietary memory card modules (not DIMMs or RIMMs we are accustomed to) that are dual ported and run at 400MHz x2... Apple would not be using these, they would go with what is the standard be it DDR or DDR-II in the future.
It is a technical article from IBM discussing the Power4 on which the GPUL is based. It sounds like the GPUL will be one core and one of three L2 caches from the Power4. The amount of data and instruction L1 caches are the same in this article as the above rumor.
I have yet to see someone give an authoritative answer to the question of who has the rights to Altivec. People here keep restating as fact that IBM can freely use it or as fact that Motorola holds the exclusive rights. Can someone show me something that says exactly which is the case? I wonder if it is something in between. IBM can use the instructions but not the silicon layout. I.E. they have to design their own version of the instructions. (Although it would seem easier to just pay Motorola than to do that.)
If they had complete rights, it would seem that the GPUL would be a matter of marrying a single Power4 core to an Altivec unit. That would certainly be a lot less work than recreating the whole thing. It would also point to a quicker release date.</strong><hr></blockquote>
I saw information talking about IBM's implimentation of VMX that made mention of 2 new SIMD registers that are identicle to Altivec's implimentation. One was VSAVE and the other escapes me at the moment. I will try and rememebr or when I return to work Monday I will update this...
Also looks like their implimentation will have a VMX unit with 2 sub units; a permute and ALU unit for the SIMD operations. What I can understand of it looks like it WILL have it's own registers and not share the FXU/FPU registers that was speculated before.
. . . who has the rights to Altivec. People here keep restating as fact that IBM can freely use it or as fact that Motorola holds the exclusive rights. Can someone show me something that says exactly which is the case? I wonder if it is something in between. IBM can use the instructions but not the silicon layout. . .
</strong><hr></blockquote>
Someone searched patents on the vector unit, and all the original patents have Apple, IBM and Motorola on them. Later patents have IBM only. Sorry I don't keep links to this stuff. Anyway, the work has been done on a new version of Apple's Velocity Engine, and from what Outsider says, IBM's VMX may be the better implementation.
I have yet to see someone give an authoritative answer to the question of who has the rights to Altivec. People here keep restating as fact that IBM can freely use it or as fact that Motorola holds the exclusive rights. Can someone show me something that says exactly which is the case?
"IBM will also add a SIMD engine to some of its upcoming PowerPC chips. SIMD, which stands for "single instruction, multiple data," breaks up certain types of data to process it in multiple, parallel chunks. IBM has the option to adopt Altivec, the multimedia SIMD engine used now by Motorola. Parker declined to comment on whether IBM would do so."
the reporter was interviewing Dean Parker, IBM's PowerPC product marketing manager.
authoritative, I don't know. Parker did not say they could use Altivec per se, but the interviewer did and Parker "declined to comment on whether IBM would do so"
"Asked whether IBM will develop a PowerPC that includes an AltiVec coprocessor, Elliott Newcombe, PowerPC product marketing manager at IBM's Research Triangle Park facility, said IBM is considering adding an AltiVec APU to one of IBM's designs.
"AltiVec could be an example of one of these coprocessors that could be plugged in [to a Book E-compliant PowerPC]," Newcombe said. "Nothing precludes IBM from doing that, but I cannot comment on whether a design is in progress. The market will decide whether we do that, and I can just say 'stay tuned.' "
This is a direct quote from an IBM representative,Elliott Newcombe, PowerPC product marketing manager at IBM's Research Triangle Park facility.
<strong>What good reason was there for Apple to do a major overhaul of the PowerMac internals recently, focusing on a massive upgrade in cooling?</strong><hr></blockquote>
Who knows, but it's nonsensical to speculate that they did this to accomodate an as-yet-unreleased chip. If they needed the change for this new chip then they'd do it when the chip was released.
Apple had a code name for a project named after Sagan, and Sagan, like a big baby, sued them for it. Must have been a DOS lover or something. Anyway, Apple changed the codename and replaced it with BHA (for Butt Headed Astronomer). True story!
Sort of like the rumors last year of G5s at 1.2, 1.4, and 1.6 GHz. A clever ruse played on the internet Mac community. Someone will get a great laugh out of this new 8500 rumor.</strong><hr></blockquote>
It may not be the 8500, but we should be seeing a G4++ with new mobo, FSB and DDR from Moto in Jan. Maybe some confusion leading some to think 8500.
pardon me, my lorcet just kicked in (mmm opiate painkillers)....
To be a bit processor-agnostic: Intel and AIM have been trading speed jumps in roughly 3-4 year alternating leaps. Pentiums, etc leapfrogged by G3 (remember the snail ads - and the time when the PhotoShop Macworld gag was not a completely contrived example?), then over the next 3-4 years Intel caught up and leaped ahead (in mhz and some performance areas). It's now about the right time for an AIM comeback.
Remember, these guys don't trade superiority in processing power every few years out of politeness. It takes that long to bring around a true quantum leap, even if kludged together like the mhz of the Pentium architecture or the mobos of the last several G4s.
Thing is, Intel's leap this last time was a kludge (IS a kludge), a way to make $$$ with the marketing of MHZ.
Apple's kludge is to stay competitive - processing-wise.
Both Intel and AIM are hard at work. But it appears that AIM will make a leap First either by presenting a multi-core chip at a single-core price (the wonder of IBM's efficient and effective fabbing and design) or (and?) by introducing a new Motorola chip that really takes advantage of on-chip extras like Ethernet, Firewire, etc - drastically reducing the overall size of the machine.
Perhaps both of these can be implemented together - both setups appear to the rumormongers to be book-e compliant - hence the parts might be multiconfigurable.
How about a motherboard 1/4 to 1/2 the size of the current ones? Significant cost savings there....
Comments
Sort of like the rumors last year of G5s at 1.2, 1.4, and 1.6 GHz. A clever ruse played on the internet Mac community. Someone will get a great laugh out of this new 8500 rumor.
<strong>I think this thread has pretty much stayed on topic and is very informative....
anyway...
I just came into some information on the GPUL I am still digesting. Sometimes some juicy info can come by... But L2 cache is 512KB 8-way set associative connected by a wide bus. L1 is fully inclusive and is 32KB for data and 64KB for instruction. It is held in the L2 also.
I will try and make sense of other info.</strong><hr></blockquote>
The information is either correct or comes from sources like this:
<a href="http://www.research.ibm.com/journal/rd/461/tendler.html"; target="_blank">http://www.research.ibm.com/journal/rd/461/tendler.html</a>;
It is a technical article from IBM discussing the Power4 on which the GPUL is based. It sounds like the GPUL will be one core and one of three L2 caches from the Power4. The amount of data and instruction L1 caches are the same in this article as the above rumor.
I have yet to see someone give an authoritative answer to the question of who has the rights to Altivec. People here keep restating as fact that IBM can freely use it or as fact that Motorola holds the exclusive rights. Can someone show me something that says exactly which is the case? I wonder if it is something in between. IBM can use the instructions but not the silicon layout. I.E. they have to design their own version of the instructions. (Although it would seem easier to just pay Motorola than to do that.)
If they had complete rights, it would seem that the GPUL would be a matter of marrying a single Power4 core to an Altivec unit. That would certainly be a lot less work than recreating the whole thing. It would also point to a quicker release date.
Fact: iMac gets new display but no speed bump.
PowerMac gets minor speedbump to keepselling until Jan-march, with promotion.
Ibook and powerbook is pretty quite the last 6 months about them.
This is of course IMO.
Apple's new (Xserve/DDR Power Mac) northbridge has the name "U2".
Given the history of lawsuits againts Apple, what are the chances Bono is gonna set his lawyers loose?
Apple sued by Apple Records
Apple sued by Mckintosh
Apple sued by Carl Sagen
etc. etc.
Barto <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />
<a href="http://www.infoworld.com/articles/hn/xml/02/10/04/021004hnforum.xml?s=IDGNS:"; target="_blank">http://www.infoworld.com/articles/hn/xml/02/10/04/021004hnforum.xml?s=IDGNS:</a>;
IBM is scheduled to discuss its 64-bit PowerPC chip, which has drawn a lot of attention from the Macintosh and Linux communities. Since the PowerPC chip uses a different instruction set than chips used with Microsoft's Windows technology, it can't be used in Windows PCs. It is expected to begin its life in low-end servers, and will also appear in workstations over time, but is "the natural upgrade path for the Apple community," said Kevin Krewell, senior editor of the Microprocessor Report in San Jose.
"(The PowerPC) is the answer to the Macintosh question of 'Where do we go from here?' " Krewell said. The processor will ship in the second half of 2003, he said. An IBM spokesman would not confirm the shipping date, citing the company's policy of not discussing unannounced information.
<strong>
Chipsets have ALWAYS been evolutionary. You just can't start from scratch with something completely new. With the U2 (UniNorth IS gone, U2 is the successor) controller, we have dual ATA-100 and DDR RAM controllers. With UniNorth 7 (from memory) we had gigabit ethernet. The first g4 uninorth saw the introduction of AGP. It's always going to be gradual. The GPUL chipset will probably be like the current one but with ApplePI and maybe one or two new features.
Barto</strong><hr></blockquote>
Not true. ApplePi is a point to point switched bus from the information that was shared with me. That means at such high speeds only one device will be able to be connected to the processor via ApplePi. ApplePi runs at a 2:1 ration from the processor core speed. That means at 1.6GHz you have a bus that runs at 800MHz, 1.8GHz and it runs at 900MHz. At these speeds it suggests ApplePi has a narrow bus width (16-32bit, my money is at 16bit) and it is based on a known standard like HyperTransport or RapidIO. Unlike MPX you will have only one direct connection to a device.
The information I got also made strong suggestions that the memory controller was NOT on die like previously suggested but the processor has a memory controller interface to connect to an external memory controller. This is good because finally the bus has enough bandwidth to supply the processor with memory bandwidth and it gives the system maker the freedom to use whatever memory technology they wish (DDR, DDR-II, RAMbus, etc.). POWER4 systems use proprietary memory card modules (not DIMMs or RIMMs we are accustomed to) that are dual ported and run at 400MHz x2... Apple would not be using these, they would go with what is the standard be it DDR or DDR-II in the future.
<strong>
The information is either correct or comes from sources like this:
<a href="http://www.research.ibm.com/journal/rd/461/tendler.html"; target="_blank">http://www.research.ibm.com/journal/rd/461/tendler.html</a>;
It is a technical article from IBM discussing the Power4 on which the GPUL is based. It sounds like the GPUL will be one core and one of three L2 caches from the Power4. The amount of data and instruction L1 caches are the same in this article as the above rumor.
I have yet to see someone give an authoritative answer to the question of who has the rights to Altivec. People here keep restating as fact that IBM can freely use it or as fact that Motorola holds the exclusive rights. Can someone show me something that says exactly which is the case? I wonder if it is something in between. IBM can use the instructions but not the silicon layout. I.E. they have to design their own version of the instructions. (Although it would seem easier to just pay Motorola than to do that.)
If they had complete rights, it would seem that the GPUL would be a matter of marrying a single Power4 core to an Altivec unit. That would certainly be a lot less work than recreating the whole thing. It would also point to a quicker release date.</strong><hr></blockquote>
I saw information talking about IBM's implimentation of VMX that made mention of 2 new SIMD registers that are identicle to Altivec's implimentation. One was VSAVE and the other escapes me at the moment. I will try and rememebr or when I return to work Monday I will update this...
Also looks like their implimentation will have a VMX unit with 2 sub units; a permute and ALU unit for the SIMD operations. What I can understand of it looks like it WILL have it's own registers and not share the FXU/FPU registers that was speculated before.
<strong>
. . . who has the rights to Altivec. People here keep restating as fact that IBM can freely use it or as fact that Motorola holds the exclusive rights. Can someone show me something that says exactly which is the case? I wonder if it is something in between. IBM can use the instructions but not the silicon layout. . .
</strong><hr></blockquote>
Someone searched patents on the vector unit, and all the original patents have Apple, IBM and Motorola on them. Later patents have IBM only. Sorry I don't keep links to this stuff. Anyway, the work has been done on a new version of Apple's Velocity Engine, and from what Outsider says, IBM's VMX may be the better implementation.
<strong>
I have yet to see someone give an authoritative answer to the question of who has the rights to Altivec. People here keep restating as fact that IBM can freely use it or as fact that Motorola holds the exclusive rights. Can someone show me something that says exactly which is the case?
</strong><hr></blockquote>
<a href="http://news.com.com/2100-1001-257421.html?legacy=cnet"; target="_blank">IBM pushes to 2GHz </a>
quote from the article
"IBM will also add a SIMD engine to some of its upcoming PowerPC chips. SIMD, which stands for "single instruction, multiple data," breaks up certain types of data to process it in multiple, parallel chunks. IBM has the option to adopt Altivec, the multimedia SIMD engine used now by Motorola. Parker declined to comment on whether IBM would do so."
the reporter was interviewing Dean Parker, IBM's PowerPC product marketing manager.
authoritative, I don't know. Parker did not say they could use Altivec per se, but the interviewer did and Parker "declined to comment on whether IBM would do so"
Found another one
<a href="http://www.eet.com/story/OEG19990507S0003"; target="_blank">IBM, Motorola write Book E on the PowerPC</a>
quote from the article
"Asked whether IBM will develop a PowerPC that includes an AltiVec coprocessor, Elliott Newcombe, PowerPC product marketing manager at IBM's Research Triangle Park facility, said IBM is considering adding an AltiVec APU to one of IBM's designs.
"AltiVec could be an example of one of these coprocessors that could be plugged in [to a Book E-compliant PowerPC]," Newcombe said. "Nothing precludes IBM from doing that, but I cannot comment on whether a design is in progress. The market will decide whether we do that, and I can just say 'stay tuned.' "
This is a direct quote from an IBM representative,Elliott Newcombe, PowerPC product marketing manager at IBM's Research Triangle Park facility.
also notice the dates of the articles.
[ 10-05-2002: Message edited by: rickag ]</p>
I still staying tuned.
<strong>Oh we haven't seen that gif yet. Thanks for sharing.</strong><hr></blockquote>
Which one? This one?
[Yes, that one. If you have nothing to contribute, contribute nothing. -Amorph]
[ 10-05-2002: Message edited by: Amorph ]</p>
<strong>What good reason was there for Apple to do a major overhaul of the PowerMac internals recently, focusing on a massive upgrade in cooling?</strong><hr></blockquote>
Who knows, but it's nonsensical to speculate that they did this to accomodate an as-yet-unreleased chip. If they needed the change for this new chip then they'd do it when the chip was released.
<strong>Swinging back to chipsets for a second.
Apple's new (Xserve/DDR Power Mac) northbridge has the name "U2".
Given the history of lawsuits againts Apple, what are the chances Bono is gonna set his lawyers loose?
Apple sued by Apple Records
Apple sued by Mckintosh
Apple sued by Carl Sagen
etc. etc.
Barto <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" /> </strong><hr></blockquote>
What did Carl Sagen sue Apple for?
<strong>Moto 8500? January? LOL!
Sort of like the rumors last year of G5s at 1.2, 1.4, and 1.6 GHz. A clever ruse played on the internet Mac community. Someone will get a great laugh out of this new 8500 rumor.</strong><hr></blockquote>
It may not be the 8500, but we should be seeing a G4++ with new mobo, FSB and DDR from Moto in Jan. Maybe some confusion leading some to think 8500.
There were 3 original Power Macs.
The 6100 - PDM
The 7100 - Carl Sagan
The 8100 - Cold Fusion
Now, PDM stood for PiltDown Man. Carl Sagan didn't appreciate that he was lumped in with two discredited "discoveries".
So, he sued Apple over it.
The Apple engineers changed the 7100's code name to BHA.
Things went quiet for a bit.
Then Carl found out BHA stood for Butt Headed Astronomer <img src="graemlins/lol.gif" border="0" alt="[Laughing]" />
He was not happy, and Apple lawyers insisted the code-name be changed AGAIN. So it was renamed LAW, for Lawyers Are Wimps.
Barto
To be a bit processor-agnostic: Intel and AIM have been trading speed jumps in roughly 3-4 year alternating leaps. Pentiums, etc leapfrogged by G3 (remember the snail ads - and the time when the PhotoShop Macworld gag was not a completely contrived example?), then over the next 3-4 years Intel caught up and leaped ahead (in mhz and some performance areas). It's now about the right time for an AIM comeback.
Remember, these guys don't trade superiority in processing power every few years out of politeness. It takes that long to bring around a true quantum leap, even if kludged together like the mhz of the Pentium architecture or the mobos of the last several G4s.
Thing is, Intel's leap this last time was a kludge (IS a kludge), a way to make $$$ with the marketing of MHZ.
Apple's kludge is to stay competitive - processing-wise.
Both Intel and AIM are hard at work. But it appears that AIM will make a leap First either by presenting a multi-core chip at a single-core price (the wonder of IBM's efficient and effective fabbing and design) or (and?) by introducing a new Motorola chip that really takes advantage of on-chip extras like Ethernet, Firewire, etc - drastically reducing the overall size of the machine.
Perhaps both of these can be implemented together - both setups appear to the rumormongers to be book-e compliant - hence the parts might be multiconfigurable.
How about a motherboard 1/4 to 1/2 the size of the current ones? Significant cost savings there....
Just drugged up ranting: Flame ON!