On the subject of Apple phasing out Moto altogether. Interesting idea from the point of view that if IBM gets all Apple's business the it's helping IBM pay for the R n' D on their Chips in a big way...chips that IBM is commited to developing anyhow. It's a big saver for IBM and it gives Apple a long term CPU partner who's not only 'on the ball' but running with it as well.
I don't see the 'GPUL' being 'only' 1 core as a problem. A single core is offering twice the performance at 1 gig. And IBM is aiming for a launch of 2 gig! Giving four times the performance. 8 way superscaler (a much needed extra fpu...), A (AN) altivec unit...and 6.4 gig bandwidth? Put it in Dual processor configurations JD...and the last several years of 'G4 ness' will seem like the bleeding dark ages.
Recent 'performance tests' show the G4 to be just behind the almost latest x86 chips... at a hefty premium...in dual configs...
PPC goes from 'hanging in there' to being 'on the edge'.
Some people are saying the 'Hammer' will give a '30%' performance increase over the last 'xp' socket processor AMD offers 'early' next year.
The 'GPUL' on the other hand is offering 4 times the current performance: removing the current bandwidth block, a kickstart to mhz (as transparent as that is...), more performance per cycle, a chip that is 64 bit and compatible with whats out there (nominal performance hit worst case scenario...), extra fpu performance for Lightwave fans (hi mum!), and then, (oh mamma, somebody stop me...) dual performance of said?
If you throw in some mood music from Moki...I'll tear your arm off for that machine.
Lemon Bon Bon
PS. I kinda think the 'single core' will probably have 'Powerbook' users reaching for the 'Joyball'... (Woody Allen ref'.)
<strong>I prefer a single core architecture with a good altivec unit totally independant, than a dual core architecture with bad tricks in order to save transistors.
A single core means less transistors and less heat. With 50 millions of transistors you can make a very sophisticated single core chip, that can be use in The I mac and powerbook line some months later.
If the chip is a dual core, we will have to wait a long time before seing it in a I mac or a powerbooK . Apple sell more I mac than powermac, it's very important for him to have good processors for all his product line.</strong><hr></blockquote>
Why does it matter if Apple uses one dual core chip or 2 single core chips in their PowerMacs? The new PowerMacs released last quarter have 2 processor across the board. If IBM can keep the transistor count under control (the new POWER4 will have one third the cache and no on die memory controller, not to mention have half the pin out of the full POWER4) then the new POWER4 will have reasonable power consumption and heat output considering 1. it will be made on a 130nm process, 2. Much less transistor count, 3. no need for costly dual processor cards.
edit: And another thing, it doesn't say sources said the chip will be single core... this appears to be speculation on the authors part.
<strong>And another thing, it doesn't say sources said the chip will be single core... this appears to be speculation on the authors part.</strong><hr></blockquote>
Yep... I too noticed that. I filed it in the same circular bin as I did the comment from Ryan @ MOSR about the GPUL code name being made up by rumor-mongers.
Next week will tell the tale... I for one can't wait.
For those who think that MOT is gonna have one last 'bang' before the GPUL it sure seems strange that we haven't seen any (interesting) leaks about it. You'd think with all the 'chatter' about GPUL someone would leak even a little info just so people would start speculating about MOTs offering as well (just to help defuse the GPUL-lust we have now) otherwise many might just look at any MOT update as a 'last who-rah' (can anyone say B&W G3 or Yikes) before the GPUL boxes come out and pass on buying them.
Now all that goes out the window if the next offering from MOT can 'run in the same pack' as a GPUL but if that's that case then why would Apple move to the GPUL in the first place and I for one really think Apple will...
<strong>(can anyone say B&W G3 or Yikes)...</strong><hr></blockquote>
In retrospect the B&W G3 was a stepping stone to the G4 (isn't anything?), but the B&W was announced and shipped 9 months before the G4 graphite was announced (and I don't think they started shipping until well into September).
If there's a message here it's that you don't get major revisions at Apple in less than 9 months.
As to Yikes - this was even more clearly, in retrospect, a fudge by Apple, who had a new chip but no new boards in production. So they announced a new "G4" - with essentially the B&W board - with the two higher end machines to follow.
We know what happened - Motorola couldn't ship the chips, so everthing got despec'd by 50MHz. But Yikes was not a new board, it was just a minor revision, Sawtooth was the new board.
Why does it matter if Apple uses one dual core chip or 2 single core chips in their PowerMacs? The new PowerMacs released last quarter have 2 processor across the board. If IBM can keep the transistor count under control (the new POWER4 will have one third the cache and no on die memory controller, not to mention have half the pin out of the full POWER4) then the new POWER4 will have reasonable power consumption and heat output considering 1. it will be made on a 130nm process, 2. Much less transistor count, 3. no need for costly dual processor cards.
edit: And another thing, it doesn't say sources said the chip will be single core... this appears to be speculation on the authors part.
The power 4 chips have not altivec and have more than 174 millions transistors, even if you reduce the cache from 1,5 to 512 (this will save 10 millions transistors approximatively) make a simpler L3 cache controller (won't save much transistors) you can save 70 millions of transistors max. And you will add some millions more with the altivec unit, even if this altivec unit share transistros with the integer and fp unit. I'll say that you cannot have a chip under 100 millions transistors.
This chip is too huge for the ti book and the i mac on SOI 0,13.
Now let's consider a one core altivec VMX chip of 50-60 millions transistors : you can have dual for the powermac and single for the ti book and the i book : there is no need for the G4 line anymore (after a period of transition). This only one core , will be more deeply pipelined than the 7455 or even the Athlon, thus allowing greater speed especially on SOI 0,13. We should see a 2 ghz chip at the end of 2003 : i don't think it's a overoptimistic guess.
May be the one core chip is only a rumor or speculation but it's a logical one.
Now all that goes out the window if the next offering from MOT can 'run in the same pack' as a GPUL but if that's that case then why would Apple move to the GPUL in the first place?</strong><hr></blockquote>
Because the GPUL has a future.
I think "dual core" would have been mentioned in the MDF talk brief. Its not so I'm assuming single core until the 15th. <rampant unfounded speculation heresay mode on> Then again perhaps IBM wants to use it in a variety of machines and will have single, dual, ternary and quad versions of the processor. Apple could then have SMP machines without having to worry about shared bus, cache snooping hardware, multiple ports on the memory controller, etc. If the GPUL is a mere 60 million transistors then a 4-way SMP version would be a mere 240 million transistors which is not unreasonable considering it is on a smaller process than the 170 million transistor POWER4.<rush mode off>
The power 4 chips have not altivec and have more than 174 millions transistors, even if you reduce the cache from 1,5 to 512 (this will save 10 millions transistors approximatively) make a simpler L3 cache controller (won't save much transistors) you can save 70 millions of transistors max. And you will add some millions more with the altivec unit, even if this altivec unit share transistros with the integer and fp unit. I'll say that you cannot have a chip under 100 millions transistors.
This chip is too huge for the ti book and the i mac on SOI 0,13.
Now let's consider a one core altivec VMX chip of 50-60 millions transistors : you can have dual for the powermac and single for the ti book and the i book : there is no need for the G4 line anymore (after a period of transition). This only one core , will be more deeply pipelined than the 7455 or even the Athlon, thus allowing greater speed especially on SOI 0,13. We should see a 2 ghz chip at the end of 2003 : i don't think it's a overoptimistic guess.
May be the one core chip is only a rumor or speculation but it's a logical one.</strong><hr></blockquote>
A few pieces of semiconductor design data. Caches are built using static RAM cells, each one takes 6 transistors, not just one transistor. Associated with the caches are the tags, which store data about what memory address is held where in the cache etc., these also take considerable resources.
Removing one megabyte of L2 cache could be expected to reduce transistor count by about 60 million transistors. Removing the L3 cache controller, because of the on-chip tags etc. could be expected to lose another 10-20 million (it is a very big L3).
A lot of transistors could also be saved by removing the high speed, wide, buses for inter- and intra-MCM communication, as well as the GX control bus.
My estimate would be a single core/512kB L2/VMX chip with hypertransport at about 65 million, dual core/512kB L2/VMX etc. at about 90 million. Together with a process change to 0.13 micron, I would expect the dual core to dissipate about 1/4 to 1/3 the power of the power4 at the same frequency, the single core about 1/6 to 1/4. I can't find the power dissipation of the POWER4 to hand at the moment, but I believe it is about 120W @ 1.3GHz.
Well our estimations are near : 100 versus 90 millions transistors for the dual, 50-60 versus 65 for the single.
Perhaps there will be dual or even quad SMP chip in the future (it will be a rather good way of improving performance of the chip without too much R&D), but i think they can start to ship a single core.
Considering the cache yes in principle , it's static ram with 5 to 6 transistors by cellular memory unit. But i am not sure it's true for on die cache : the 512 K cache of the sahara chip will need 30 millions transistors by it self, i don't remember the number of transistors of this chip, but i am nearly sure it's less than this number. Perhaps some others people may bring us an answer.
According to IBM's press release about the Fishkill plant, they'll start at .13 and move within months to .09. So a single core might debut, with a dual core following not long after. Or, if it is (and remains) single core, it will become suitable for portable use not long after its introduction.
The new Fishkill fab is barely operational (not barely working, but fab capacity is not being used at this moment). The old fab is being kept in operation past its supposed shut down date.
<strong>Well our estimations are near : 100 versus 90 millions transistors for the dual, 50-60 versus 65 for the single.
Perhaps there will be dual or even quad SMP chip in the future (it will be a rather good way of improving performance of the chip without too much R&D), but i think they can start to ship a single core.
Considering the cache yes in principle , it's static ram with 5 to 6 transistors by cellular memory unit. But i am not sure it's true for on die cache : the 512 K cache of the sahara chip will need 30 millions transistors by it self, i don't remember the number of transistors of this chip, but i am nearly sure it's less than this number. Perhaps some others people may bring us an answer.</strong><hr></blockquote>
Yes but look at this picture of the present POWER4 die:
The lower half is the caches (L2) and too the far left lower half is the L3 tags. Between the tags are the L3 controller circuits. There are 3 banks of 512KB L2 to make 1.5MB. Take away 2/3 and you cut it by 35%. the L3 supports up to 32MB L3 cache per chip. Thats a lot of L3 cache. Even if the new POWER4 has L3 cache it would be more in the 4MB range and there would be much less L3 tags. Even factoring the added transistors for VMX you are only operating with about 60% of the transistors of the POWER4.
Yes but look at this picture of the present POWER4 die:
The lower half is the caches (L2) and too the far left lower half is the L3 tags. Between the tags are the L3 controller circuits. There are 3 banks of 512KB L2 to make 1.5MB. Take away 2/3 and you cut it by 35%. the L3 supports up to 32MB L3 cache per chip. Thats a lot of L3 cache. Even if the new POWER4 has L3 cache it would be more in the 4MB range and there would be much less L3 tags. Even factoring the added transistors for VMX you are only operating with about 60% of the transistors of the POWER4.</strong><hr></blockquote>
Nice picture, I love the symmetry of the two cores in the top half. I'm hoping for both single and dual core versions, but not sanguine given the ultra-light nomenclature.
There would be considerable cost advantages to a dual core chip over two single core chips as it would probably have the same pinout, or at least interface, a lot less work for the circuit designers and chipset people, as well as reducing inventory.
Just to add a few things the next PIV produced on the 0.09µm process is around 100 million transistors. Is it possible what they will do is start with a single core on a 0.13µm process then switch across?
The problem I'd see there is the extra effort involved. If transistor count was your sole concern though you could certainly get around it that way.
Personally I would expect a dual core CPU would be preferable to 2 separate CPUs though.
Just to chime in on the Dual / Single core issue...
I (unfortunately) don't have any info on the GPUL, but I do know that IBM currently produces all Power4's with dual cores (this you already knew). However, they find quite a few chips with only one core fully functional, the other has defects.
They still use the single core chips.
This is just another option they have with the GPUL: produce duals, and sell both dual and singles, thus increasing yeild.
Going forward I think we'll see more and more multi-way chips -- this is described in a paper by an engineer at IBM as the "cellular approach". A single chip with 16 or 32 cores on it is not unreasonable when we can put a billion transistors on a die. At that point chips will probably be sold based on what clock rate they perform at (just like today) and how many working processors they have. IBM has already started this by using defective duals as singles.
Yep... I too noticed that. I filed it in the same circular bin as I did the comment from Ryan @ MOSR about the GPUL code name being made up by rumor-mongers.
Next week will tell the tale... I for one can't wait.
For those who think that MOT is gonna have one last 'bang' before the GPUL it sure seems strange that we haven't seen any (interesting) leaks about it. You'd think with all the 'chatter' about GPUL someone would leak even a little info just so people would start speculating about MOTs offering as well (just to help defuse the GPUL-lust we have now) otherwise many might just look at any MOT update as a 'last who-rah' (can anyone say B&W G3 or Yikes) before the GPUL boxes come out and pass on buying them.
Now all that goes out the window if the next offering from MOT can 'run in the same pack' as a GPUL but if that's that case then why would Apple move to the GPUL in the first place and I for one really think Apple will...
I've mentioned my info a few times. A G4++ of sorts with new mobo, faster FSB and DDR in Jan. The mobo has been having major heat issues which may explain the vents on the current towers. I would guess up to around 1.4ghz. The GPUL is set for fall release.
Comments
I don't see the 'GPUL' being 'only' 1 core as a problem. A single core is offering twice the performance at 1 gig. And IBM is aiming for a launch of 2 gig! Giving four times the performance. 8 way superscaler (a much needed extra fpu...), A (AN) altivec unit...and 6.4 gig bandwidth? Put it in Dual processor configurations JD...and the last several years of 'G4 ness' will seem like the bleeding dark ages.
Recent 'performance tests' show the G4 to be just behind the almost latest x86 chips... at a hefty premium...in dual configs...
PPC goes from 'hanging in there' to being 'on the edge'.
Some people are saying the 'Hammer' will give a '30%' performance increase over the last 'xp' socket processor AMD offers 'early' next year.
The 'GPUL' on the other hand is offering 4 times the current performance: removing the current bandwidth block, a kickstart to mhz (as transparent as that is...), more performance per cycle, a chip that is 64 bit and compatible with whats out there (nominal performance hit worst case scenario...), extra fpu performance for Lightwave fans (hi mum!), and then, (oh mamma, somebody stop me...) dual performance of said?
If you throw in some mood music from Moki...I'll tear your arm off for that machine.
Lemon Bon Bon
PS. I kinda think the 'single core' will probably have 'Powerbook' users reaching for the 'Joyball'... (Woody Allen ref'.)
[ 10-10-2002: Message edited by: Lemon Bon Bon ]
[ 10-10-2002: Message edited by: Lemon Bon Bon ]
[ 10-10-2002: Message edited by: Lemon Bon Bon ]</p>
<strong>I prefer a single core architecture with a good altivec unit totally independant, than a dual core architecture with bad tricks in order to save transistors.
A single core means less transistors and less heat. With 50 millions of transistors you can make a very sophisticated single core chip, that can be use in The I mac and powerbook line some months later.
If the chip is a dual core, we will have to wait a long time before seing it in a I mac or a powerbooK . Apple sell more I mac than powermac, it's very important for him to have good processors for all his product line.</strong><hr></blockquote>
Why does it matter if Apple uses one dual core chip or 2 single core chips in their PowerMacs? The new PowerMacs released last quarter have 2 processor across the board. If IBM can keep the transistor count under control (the new POWER4 will have one third the cache and no on die memory controller, not to mention have half the pin out of the full POWER4) then the new POWER4 will have reasonable power consumption and heat output considering 1. it will be made on a 130nm process, 2. Much less transistor count, 3. no need for costly dual processor cards.
edit: And another thing, it doesn't say sources said the chip will be single core... this appears to be speculation on the authors part.
[ 10-10-2002: Message edited by: Outsider ]</p>
<strong>And another thing, it doesn't say sources said the chip will be single core... this appears to be speculation on the authors part.</strong><hr></blockquote>
Yep... I too noticed that. I filed it in the same circular bin as I did the comment from Ryan @ MOSR about the GPUL code name being made up by rumor-mongers.
Next week will tell the tale... I for one can't wait.
For those who think that MOT is gonna have one last 'bang' before the GPUL it sure seems strange that we haven't seen any (interesting) leaks about it. You'd think with all the 'chatter' about GPUL someone would leak even a little info just so people would start speculating about MOTs offering as well (just to help defuse the GPUL-lust we have now) otherwise many might just look at any MOT update as a 'last who-rah' (can anyone say B&W G3 or Yikes) before the GPUL boxes come out and pass on buying them.
Now all that goes out the window if the next offering from MOT can 'run in the same pack' as a GPUL but if that's that case then why would Apple move to the GPUL in the first place and I for one really think Apple will...
Dave
[ 10-10-2002: Message edited by: DaveGee ]</p>
<strong>(can anyone say B&W G3 or Yikes)...</strong><hr></blockquote>
In retrospect the B&W G3 was a stepping stone to the G4 (isn't anything?), but the B&W was announced and shipped 9 months before the G4 graphite was announced (and I don't think they started shipping until well into September).
If there's a message here it's that you don't get major revisions at Apple in less than 9 months.
As to Yikes - this was even more clearly, in retrospect, a fudge by Apple, who had a new chip but no new boards in production. So they announced a new "G4" - with essentially the B&W board - with the two higher end machines to follow.
We know what happened - Motorola couldn't ship the chips, so everthing got despec'd by 50MHz. But Yikes was not a new board, it was just a minor revision, Sawtooth was the new board.
<strong>
Why does it matter if Apple uses one dual core chip or 2 single core chips in their PowerMacs? The new PowerMacs released last quarter have 2 processor across the board. If IBM can keep the transistor count under control (the new POWER4 will have one third the cache and no on die memory controller, not to mention have half the pin out of the full POWER4) then the new POWER4 will have reasonable power consumption and heat output considering 1. it will be made on a 130nm process, 2. Much less transistor count, 3. no need for costly dual processor cards.
edit: And another thing, it doesn't say sources said the chip will be single core... this appears to be speculation on the authors part.
[ 10-10-2002: Message edited by: Outsider ]</strong><hr></blockquote>
The power 4 chips have not altivec and have more than 174 millions transistors, even if you reduce the cache from 1,5 to 512 (this will save 10 millions transistors approximatively) make a simpler L3 cache controller (won't save much transistors) you can save 70 millions of transistors max. And you will add some millions more with the altivec unit, even if this altivec unit share transistros with the integer and fp unit. I'll say that you cannot have a chip under 100 millions transistors.
This chip is too huge for the ti book and the i mac on SOI 0,13.
Now let's consider a one core altivec VMX chip of 50-60 millions transistors : you can have dual for the powermac and single for the ti book and the i book : there is no need for the G4 line anymore (after a period of transition). This only one core , will be more deeply pipelined than the 7455 or even the Athlon, thus allowing greater speed especially on SOI 0,13. We should see a 2 ghz chip at the end of 2003 : i don't think it's a overoptimistic guess.
May be the one core chip is only a rumor or speculation but it's a logical one.
<strong>
Now all that goes out the window if the next offering from MOT can 'run in the same pack' as a GPUL but if that's that case then why would Apple move to the GPUL in the first place?</strong><hr></blockquote>
Because the GPUL has a future.
I think "dual core" would have been mentioned in the MDF talk brief. Its not so I'm assuming single core until the 15th. <rampant unfounded speculation heresay mode on> Then again perhaps IBM wants to use it in a variety of machines and will have single, dual, ternary and quad versions of the processor. Apple could then have SMP machines without having to worry about shared bus, cache snooping hardware, multiple ports on the memory controller, etc. If the GPUL is a mere 60 million transistors then a 4-way SMP version would be a mere 240 million transistors which is not unreasonable considering it is on a smaller process than the 170 million transistor POWER4.<rush mode off>
<strong>will be more deeply pipelined than the 7455 or even the Athlon, thus allowing greater speed especially on SOI 0,13.</strong><hr></blockquote>
Surely pipeline depth is analagous to clock cycle, not speed!?
Â*Â*Â*Â*Â*http://www.apple.com/promo/office/
Promo finishes 07/01/2003 - must mean new PowerMacs for MWSF!? (doesn't mean anything of the sort, but some might sayÂ?)
would give fresh lineup to both chips and keep marketing needs easy.
"MacOS X running on a 2x X2 config bundled with MS Office v.X" ... hmm, how much X could woodchuck X if a woo.. nevermind
hehe.. I like the dual X2 chip as 2X X2. Symmetry. Niiiice.
<strong>
The power 4 chips have not altivec and have more than 174 millions transistors, even if you reduce the cache from 1,5 to 512 (this will save 10 millions transistors approximatively) make a simpler L3 cache controller (won't save much transistors) you can save 70 millions of transistors max. And you will add some millions more with the altivec unit, even if this altivec unit share transistros with the integer and fp unit. I'll say that you cannot have a chip under 100 millions transistors.
This chip is too huge for the ti book and the i mac on SOI 0,13.
Now let's consider a one core altivec VMX chip of 50-60 millions transistors : you can have dual for the powermac and single for the ti book and the i book : there is no need for the G4 line anymore (after a period of transition). This only one core , will be more deeply pipelined than the 7455 or even the Athlon, thus allowing greater speed especially on SOI 0,13. We should see a 2 ghz chip at the end of 2003 : i don't think it's a overoptimistic guess.
May be the one core chip is only a rumor or speculation but it's a logical one.</strong><hr></blockquote>
A few pieces of semiconductor design data. Caches are built using static RAM cells, each one takes 6 transistors, not just one transistor. Associated with the caches are the tags, which store data about what memory address is held where in the cache etc., these also take considerable resources.
Removing one megabyte of L2 cache could be expected to reduce transistor count by about 60 million transistors. Removing the L3 cache controller, because of the on-chip tags etc. could be expected to lose another 10-20 million (it is a very big L3).
A lot of transistors could also be saved by removing the high speed, wide, buses for inter- and intra-MCM communication, as well as the GX control bus.
My estimate would be a single core/512kB L2/VMX chip with hypertransport at about 65 million, dual core/512kB L2/VMX etc. at about 90 million. Together with a process change to 0.13 micron, I would expect the dual core to dissipate about 1/4 to 1/3 the power of the power4 at the same frequency, the single core about 1/6 to 1/4. I can't find the power dissipation of the POWER4 to hand at the moment, but I believe it is about 120W @ 1.3GHz.
michael
Perhaps there will be dual or even quad SMP chip in the future (it will be a rather good way of improving performance of the chip without too much R&D), but i think they can start to ship a single core.
Considering the cache yes in principle , it's static ram with 5 to 6 transistors by cellular memory unit. But i am not sure it's true for on die cache : the 512 K cache of the sahara chip will need 30 millions transistors by it self, i don't remember the number of transistors of this chip, but i am nearly sure it's less than this number. Perhaps some others people may bring us an answer.
<strong>Well our estimations are near : 100 versus 90 millions transistors for the dual, 50-60 versus 65 for the single.
Perhaps there will be dual or even quad SMP chip in the future (it will be a rather good way of improving performance of the chip without too much R&D), but i think they can start to ship a single core.
Considering the cache yes in principle , it's static ram with 5 to 6 transistors by cellular memory unit. But i am not sure it's true for on die cache : the 512 K cache of the sahara chip will need 30 millions transistors by it self, i don't remember the number of transistors of this chip, but i am nearly sure it's less than this number. Perhaps some others people may bring us an answer.</strong><hr></blockquote>
Yes but look at this picture of the present POWER4 die:
The lower half is the caches (L2) and too the far left lower half is the L3 tags. Between the tags are the L3 controller circuits. There are 3 banks of 512KB L2 to make 1.5MB. Take away 2/3 and you cut it by 35%. the L3 supports up to 32MB L3 cache per chip. Thats a lot of L3 cache. Even if the new POWER4 has L3 cache it would be more in the 4MB range and there would be much less L3 tags. Even factoring the added transistors for VMX you are only operating with about 60% of the transistors of the POWER4.
<strong>
Yes but look at this picture of the present POWER4 die:
The lower half is the caches (L2) and too the far left lower half is the L3 tags. Between the tags are the L3 controller circuits. There are 3 banks of 512KB L2 to make 1.5MB. Take away 2/3 and you cut it by 35%. the L3 supports up to 32MB L3 cache per chip. Thats a lot of L3 cache. Even if the new POWER4 has L3 cache it would be more in the 4MB range and there would be much less L3 tags. Even factoring the added transistors for VMX you are only operating with about 60% of the transistors of the POWER4.</strong><hr></blockquote>
Nice picture, I love the symmetry of the two cores in the top half. I'm hoping for both single and dual core versions, but not sanguine given the ultra-light nomenclature.
There would be considerable cost advantages to a dual core chip over two single core chips as it would probably have the same pinout, or at least interface, a lot less work for the circuit designers and chipset people, as well as reducing inventory.
michael
Thank IBM for that.
Edit: This is the <a href="http://researchweb.watson.ibm.com/journal/rd/461/tendler.html"; target="_blank">article</a> it's from just to ensure credit goes where it is due.
[ 10-10-2002: Message edited by: Telomar ]</p>
The problem I'd see there is the extra effort involved. If transistor count was your sole concern though you could certainly get around it that way.
Personally I would expect a dual core CPU would be preferable to 2 separate CPUs though.
I (unfortunately) don't have any info on the GPUL, but I do know that IBM currently produces all Power4's with dual cores (this you already knew). However, they find quite a few chips with only one core fully functional, the other has defects.
They still use the single core chips.
This is just another option they have with the GPUL: produce duals, and sell both dual and singles, thus increasing yeild.
<strong>
Yep... I too noticed that. I filed it in the same circular bin as I did the comment from Ryan @ MOSR about the GPUL code name being made up by rumor-mongers.
Next week will tell the tale... I for one can't wait.
For those who think that MOT is gonna have one last 'bang' before the GPUL it sure seems strange that we haven't seen any (interesting) leaks about it. You'd think with all the 'chatter' about GPUL someone would leak even a little info just so people would start speculating about MOTs offering as well (just to help defuse the GPUL-lust we have now) otherwise many might just look at any MOT update as a 'last who-rah' (can anyone say B&W G3 or Yikes) before the GPUL boxes come out and pass on buying them.
Now all that goes out the window if the next offering from MOT can 'run in the same pack' as a GPUL but if that's that case then why would Apple move to the GPUL in the first place and I for one really think Apple will...
Dave
[ 10-10-2002: Message edited by: DaveGee ]</strong><hr></blockquote>
I've mentioned my info a few times. A G4++ of sorts with new mobo, faster FSB and DDR in Jan. The mobo has been having major heat issues which may explain the vents on the current towers. I would guess up to around 1.4ghz. The GPUL is set for fall release.