I'm just having a hard time understanding the G4++ concept (and a really hard time with a MOT G5 concept). I say this cause I'm pretty firmly seated in the 'GPUL' (aka New IBM CPU to be intro'd at on the 15th) will be used by Apple camp.
Since I know it takes YEARS to go from paper to having real CPU, stuff like jumping from one CPU to another doesn't happen overnight (not by a long shot). Because of this IBM or MOT wouldn't just 'whip up' a new CPU and show it to a customer (Apple) and say waddya think? Wanna use it??
Building a CPU or making MAJOR changes to an existing CPU cost big money and I'm pretty sure MOT or IBM wouldn't do such a think for such a small (in CPU terms) chip run. Unless that is they had a contract for enough units to turn a profit or some kinda lock that would prevent the buyer from just backing out right after all the CPU production costs were already spent.
Let's say MOT is working on and is ready to deliver a new G4++ or G5 CPU and it'll be ready for MWSF. Okay... Apple put's it in their tower line and all is good with the world. Faster memory access more speed etc.
Summer/Fall (general guestimate of GPUL eta) what happens to the G4++ (or G5?) Would those new CPU's really cost so little that Apple could afford to move them down to the iMac line so quickly after the initial intro (usually it takes time for a new CPU price to drop)? Would the CPU be low power enough for the powerbook line (usually low power come later don't they)??? Remember MOT would have spent a fair bit of change to develop a new CPU and it's gonna need to make that money back.
I dunno but if Apple is gonna go with IBM's CPU and that CPU is gonna be ready by the summer time frame then I just don't see how a new MOT designed CPU fits.
first of all motorola will make it and ibm will manufacture it. ibm will do mass production. it will come out in 5 months. trust me I know cause my friend wroks for apple.
Yea I did considered that but then the only way it can work is for Apple and MOT to not market the CPU as a 'G5' (as some say) but instead just the next G4 (G4++ as others say) since it would be 'marketing hell' to try to explain to the Apple customer base as to why the 'G5' had such a short life.
I don't think it would be a short life actually, rather a new life. I've been thinking that same thing for a while, GPuL high-end, G5 everything else.
This G5 would be small and cool, and not much more powerful than current high end G4's, but it would carry a modern FSB and and fab process, and if based on 8xxx, be a 64bit chip.
This is a good thing, as it could allow Apple to concieveably complete a transition to 64bits in the space of 18 months, much quicker than any other platform.
Even with a fast CPU finally going into the powermac, the rest of the line-up will need attention. A 1.25Ghz G4 in an iMac or PB would certainly do the business, but that remains a short term solution. There isn't much left to give on the FSB issue. Maxxing the L3 cache to 2MB and using a single CPU might let you realize some benefit to clocking the G4 to 1.5 or 1.6Ghz (on a 166 FSB), but that's really about it. Apple needs longer term viability for the rest of the line-up.
They could look to IBM to VMX a Sahara and basically create a nouveau G4, it would be small and cool, and raise the FSB to 200Mhz. That's significant, if IBM can do it, it is possible that a small tweak might also take Moto's MPX to 200. That's not bad, but it's not the greatest either.
On the other hand, having a G5 (as a G3 replacement) and a GPuL (as a G4 replacement) would allow Apple to complete a 64bit line-up, and do it in style too. Everything would run the 32 bit library perfectly, but the 64 bit library would also be open to all machines. New apps could go 64 with a lot less hesitation. Even if a G5 didnt offer significant performance boosts over current top end G4's, the marketing potential, both to the public and devs, is huge.
Is it possible that Apple could actually have flexed it's muscles as a fairly major customer of both IBM and Motorola? For the last few years, Apple has only really had Moto as their chip designer, with IBM as a contract manufacturer. This has led to a stagnation in PPC development.
I think it is possible that Apple realized that they need their 2 suppliers either working together on a project, a la the original AIM PPC specifications, or that they should compete. When AIM was around, they produced great chips and designs, but the in fighting caused problems and slowdowns. When IBM and Moto split and Moto took over Summerset facilities, we were left where we are now. So, since IBM and Moto seem unale to truely cooperate any more, perhaps it is time for competition.
I can see Apple giving both companies the opportunity to prove to Apple who will be the first to provide them with their next generation PPC. The fact that we are hearing a lot of chatter about the Moto G5( quiet now though) and the IBM GPUL, shows to me that they are both working very hard to out do the other. This level of noise about a new processor hasn't really been around since the days when AIM was strong and Exponetial was lighting a fire under their collective asses.
Ideally, I think the whomever win the final design for Apple, both companies with assume that design for manufacture and future improvements, much as they originally did at the formation of AIM, when Moro dumped theor 68xxx and went to PPC.
Motorola has publicly stated that they aren't going to try and compete in the desktop processor business. The G4 is primarily targeted at the embedded market. Motorola's embedded market does have room for a high performance chip so the G4 customers (besides Apple) will be asking for faster G4s. Moto's stated direction is to adopt the RapidIO bus, so I would not be surprised to see a process shrunk G4 w/ RapidIO bus -- the G4 is still their fastest core and making it communicate with their new bus standard seems to make sense. Alternatively they'll add AltiVec to a beefed up 8xxx core, or attach the G4 core to their OCEAN fabric. Their G4 customers are using AltiVec, and like using AltiVec, so they aren't going to just drop it. Any of these scenarios is much less than a full new processor design, all of them are targeted at Moto's primary market, and all of them could be called a G5. The low heat, low power profile would make them well suited to a laptop or iMac design. If the design is based around OCEAN and the system-on-a-chip scheme then an Apple specialized version that uses ApplePi might be feasible which would allow Apple to use the same chip interface across its entire line.
We'll soon hear about the GPUL. The 6.4 GB/sec interface is suspiciously close to the HyperTransport speed. I can see Apple prefering an off-chip memory controller just so that they have more control over system design, and since they're part of the HT Consortium this would be an obvious choice for ApplePi. From the little I know of HT it doesn't really have a protocol to allow cache coherency and processor communication, this is something that Apple could design on top of HT and brand ApplePi.
Time to put the bets on the table, gentlemen... the Microprocessor Forum is almost upon us.
<strong>We'll soon hear about the GPUL. The 6.4 GB/sec interface is suspiciously close to the HyperTransport speed. I can see Apple prefering an off-chip memory controller just so that they have more control over system design, and since they're part of the HT Consortium this would be an obvious choice for ApplePi. From the little I know of HT it doesn't really have a protocol to allow cache coherency and processor communication, this is something that Apple could design on top of HT and brand ApplePi.
Time to put the bets on the table, gentlemen... the Microprocessor Forum is almost upon us.</strong><hr></blockquote>
After looking at alot of information, I have reversed my opinion the ApplePi is based on RapidIO but rather it is a version of Hyper Transport. I don't see how they can acheive anywhere close to 6.4GBps on RIO running at speeds less than 1GHz and 16bit data paths. At 800-950MHz speeds it needs to be 32bits because if the memory controller is outside the processor die and bandwidth is shared on that bus now with memory/PCI/AGP and other peripherals, ~6.4GBp will still be pretty sufficient. If maxed out, PCI-X takes 1GBps, AGP 8X 2.1GBps, memory will still have an open 2.7-3.2GBps.
My predictions for the 15th?
GPUL will be dual core, 16 stage pipeline for the FXUs and 21 stages for the FPUs, 512KB L2, no memory controller, HT bus running ay half the core speed, with a seperate VMX unit (with exclusive registers)in each processor core. Speeds? just under 2GHz.
This is a pretty long thread here. I had to come take a look for myself. All I can say is that this all seems extremely impressive, but the last time I saw a thread like this was two MWSF's ago when everybody thought Apple would be releasing a UMA-2 w/FireWire 2 / PCI -X / DDR / USB 2.0 / and 2, or 4x GHZ+ G4+ processors.
The time before that was thread by Kormac76 that seemd to confirm every possible handheld device, and a slimline Vio-esque laptop in the future would be comming solely from Apple.
All I have to say on all this (again) is dont get your hopes up too high.
After both of these shows people were screaming all over the internet saying things like "where's my Dual 1GHz+ G4+'s, w/ firewire-2, USB 2.0, and DDR?"
As if Apple had told them that was what to expect.
Until Apple announces (or actually ship's) something. I wouldn't count on any of this stuff being in any future Mac's.
I hate to burst your bubble, or slow/change the momentum of this thread, but I thought the words of a realist were overdue in here.
Until Apple announces (or actually ship's) something. I wouldn't count on any of this stuff being in any future Mac's.
</strong><hr></blockquote>
Good advice. A couple things make this thread a little different. The chip is real and will be the topic of a presentation on October 15th. We are in the single digits now, counting down to that event, and I guess we like to speculate about details of this 64-bit wonder.
You are correct. We can't be absolutely sure that Apple will use it in a Macintosh. However, even here there is more than usual hard evidence that indicates it is highly likely. For one, consider Apple's purchase of several high end video and special effects software companies. Applications like this need workstation class hardware, and this chip is the only known PPC candidate to give such performance to the Mac. Apple is not in the habit of buying software companies to let them run the products on competing hardware.
<strong>first of all motorola will make it and ibm will manufacture it. ibm will do mass production. it will come out in 5 months. trust me I know cause my friend wroks for apple.</strong><hr></blockquote>
I realize that past experience teaches people to be skeptical when confronted with such statements, but Yoyo's assertion is actually wholly accurate in this instance. I can confirm this, as Molly, my tapeworm, has three million offspring living in Steve Jobs' intestine. More surprisingly, Molly tells me that Jobs' has been eating a lot of Taco Bell lately and has taken to washing it down with beverages from the reinvigorated Fanta soft drink line, particularly the Pineapple flavor. Of course, Steve's various bodily parasites like to gab, and a Herpes virus told one of Molly's larvae that Stevey's newfound proclivity for Fanta is, in fact, because Steve "wanna wanna" real bad.
After looking at alot of information, I have reversed my opinion the ApplePi is based on RapidIO but rather it is a version of Hyper Transport. I don't see how they can acheive anywhere close to 6.4GBps on RIO running at speeds less than 1GHz and 16bit data paths. At 800-950MHz speeds it needs to be 32bits because if the memory controller is outside the processor die and bandwidth is shared on that bus now with memory/PCI/AGP and other peripherals, ~6.4GBp will still be pretty sufficient. If maxed out, PCI-X takes 1GBps, AGP 8X 2.1GBps, memory will still have an open 2.7-3.2GBps.
My predictions for the 15th?
GPUL will be dual core, 16 stage pipeline for the FXUs and 21 stages for the FPUs, 512KB L2, no memory controller, HT bus running ay half the core speed, with a seperate VMX unit (with exclusive registers)in each processor core. Speeds? just under 2GHz.</strong><hr></blockquote>
I'm not sure why you say that the processor's bandwidth needs to be shared with all the I/O ports...? The ApplePi bus will likely connect the processor to the memory controller, and this will be integral with the I/O chipset or connected to it via another point-to-point link. I'd also expect that in an SMP machine (err, I mean multi-chip not just a single multi-core chip) the memory chipset would support one point-to-point link to each processor die. Memory bus snooping would need to happen in the chipset, or the memory controller would put all transactions on all the interconnects so that processors can snoop. Each processor die would then have a 6.4 GB/sec connection to the memory controller, and the I/O system would have its own connection(s). This is the same as the arrangement in the current DDR PowerMacs. Apple can then do whatever it wants in terms of the actual memory implementation -- DDR333/400, DDR-II, dual channel, etc. Heck, they could just put a HyperTransport connection to the video chipset (instead of AGP) and use its VRAM! 128+ MB of 20 GB/sec memory is nothing to sneeze at.
I realize that past experience teaches people to be skeptical when confronted with such statements, but Yoyo's assertion is actually wholly accurate in this instance. I can confirm this, as Molly, my tapeworm, has three million offspring living in Steve Jobs' intestine. More surprisingly, Molly tells me that Jobs' has been eating a lot of Taco Bell lately and has taken to washing it down with beverages from the reinvigorated Fanta soft drink line, particularly the Pineapple flavor. Of course, Steve's various bodily parasites like to gab, and a Herpes virus told one of Molly's larvae that Stevey's newfound proclivity for Fanta is, in fact, because Steve "wanna wanna" real bad.</strong><hr></blockquote>
Molly's a BITCH! She told me I was her only bowel....
Not to throw fuel on anything but keep in mind IBM has a roadmap for the current G3 and it is fairly reasonable. There is no real need to replace it with something from Motorola unless it is really worth it.
Comments
Since I know it takes YEARS to go from paper to having real CPU, stuff like jumping from one CPU to another doesn't happen overnight (not by a long shot). Because of this IBM or MOT wouldn't just 'whip up' a new CPU and show it to a customer (Apple) and say waddya think? Wanna use it??
Building a CPU or making MAJOR changes to an existing CPU cost big money and I'm pretty sure MOT or IBM wouldn't do such a think for such a small (in CPU terms) chip run. Unless that is they had a contract for enough units to turn a profit or some kinda lock that would prevent the buyer from just backing out right after all the CPU production costs were already spent.
Let's say MOT is working on and is ready to deliver a new G4++ or G5 CPU and it'll be ready for MWSF. Okay... Apple put's it in their tower line and all is good with the world. Faster memory access more speed etc.
Summer/Fall (general guestimate of GPUL eta) what happens to the G4++ (or G5?) Would those new CPU's really cost so little that Apple could afford to move them down to the iMac line so quickly after the initial intro (usually it takes time for a new CPU price to drop)? Would the CPU be low power enough for the powerbook line (usually low power come later don't they)??? Remember MOT would have spent a fair bit of change to develop a new CPU and it's gonna need to make that money back.
I dunno but if Apple is gonna go with IBM's CPU and that CPU is gonna be ready by the summer time frame then I just don't see how a new MOT designed CPU fits.
Maybe it's just really late and I'm exausted...
Dave
[ 10-06-2002: Message edited by: DaveGee ]</p>
So say for instance...
- We first see the Moto G5 in the Powermac...
-Then we see the IBM GPUL introduced in the Xserve..(Mid 2003)
- Then the Moto G5 moves to the Imac
- The GPUL Moves to the Powermac
- Then Moto G5 moves to PowerBook
Comprende? <img src="graemlins/oyvey.gif" border="0" alt="[No]" />
<strong>trust me I know cause my friend wroks for apple.</strong><hr></blockquote>
<img src="graemlins/oyvey.gif" border="0" alt="[No]" />
<strong>What if.... the Moto "G5" is destined to become what the G3 was (lower power/cheaper)
So say for instance...
- We first see the Moto G5 in the Powermac...
-Then we see the IBM GPUL introduced in the Xserve..(Mid 2003)
- Then the Moto G5 moves to the Imac
- The GPUL Moves to the Powermac
- Then Moto G5 moves to PowerBook
Comprende? <img src="graemlins/oyvey.gif" border="0" alt="[No]" /> </strong><hr></blockquote>
Yea I did considered that but then the only way it can work is for Apple and MOT to not market the CPU as a 'G5' (as some say) but instead just the next G4 (G4++ as others say) since it would be 'marketing hell' to try to explain to the Apple customer base as to why the 'G5' had such a short life.
Dave
This G5 would be small and cool, and not much more powerful than current high end G4's, but it would carry a modern FSB and and fab process, and if based on 8xxx, be a 64bit chip.
This is a good thing, as it could allow Apple to concieveably complete a transition to 64bits in the space of 18 months, much quicker than any other platform.
Even with a fast CPU finally going into the powermac, the rest of the line-up will need attention. A 1.25Ghz G4 in an iMac or PB would certainly do the business, but that remains a short term solution. There isn't much left to give on the FSB issue. Maxxing the L3 cache to 2MB and using a single CPU might let you realize some benefit to clocking the G4 to 1.5 or 1.6Ghz (on a 166 FSB), but that's really about it. Apple needs longer term viability for the rest of the line-up.
They could look to IBM to VMX a Sahara and basically create a nouveau G4, it would be small and cool, and raise the FSB to 200Mhz. That's significant, if IBM can do it, it is possible that a small tweak might also take Moto's MPX to 200. That's not bad, but it's not the greatest either.
On the other hand, having a G5 (as a G3 replacement) and a GPuL (as a G4 replacement) would allow Apple to complete a 64bit line-up, and do it in style too. Everything would run the 32 bit library perfectly, but the 64 bit library would also be open to all machines. New apps could go 64 with a lot less hesitation. Even if a G5 didnt offer significant performance boosts over current top end G4's, the marketing potential, both to the public and devs, is huge.
I dunno...
[ 10-06-2002: Message edited by: Matsu ]</p>
I think it is possible that Apple realized that they need their 2 suppliers either working together on a project, a la the original AIM PPC specifications, or that they should compete. When AIM was around, they produced great chips and designs, but the in fighting caused problems and slowdowns. When IBM and Moto split and Moto took over Summerset facilities, we were left where we are now. So, since IBM and Moto seem unale to truely cooperate any more, perhaps it is time for competition.
I can see Apple giving both companies the opportunity to prove to Apple who will be the first to provide them with their next generation PPC. The fact that we are hearing a lot of chatter about the Moto G5( quiet now though) and the IBM GPUL, shows to me that they are both working very hard to out do the other. This level of noise about a new processor hasn't really been around since the days when AIM was strong and Exponetial was lighting a fire under their collective asses.
Ideally, I think the whomever win the final design for Apple, both companies with assume that design for manufacture and future improvements, much as they originally did at the formation of AIM, when Moro dumped theor 68xxx and went to PPC.
Just my rambling thoughts to add to the thread,
Tulkas
We'll soon hear about the GPUL. The 6.4 GB/sec interface is suspiciously close to the HyperTransport speed. I can see Apple prefering an off-chip memory controller just so that they have more control over system design, and since they're part of the HT Consortium this would be an obvious choice for ApplePi. From the little I know of HT it doesn't really have a protocol to allow cache coherency and processor communication, this is something that Apple could design on top of HT and brand ApplePi.
Time to put the bets on the table, gentlemen... the Microprocessor Forum is almost upon us.
<strong>We'll soon hear about the GPUL. The 6.4 GB/sec interface is suspiciously close to the HyperTransport speed. I can see Apple prefering an off-chip memory controller just so that they have more control over system design, and since they're part of the HT Consortium this would be an obvious choice for ApplePi. From the little I know of HT it doesn't really have a protocol to allow cache coherency and processor communication, this is something that Apple could design on top of HT and brand ApplePi.
Time to put the bets on the table, gentlemen... the Microprocessor Forum is almost upon us.</strong><hr></blockquote>
After looking at alot of information, I have reversed my opinion the ApplePi is based on RapidIO but rather it is a version of Hyper Transport. I don't see how they can acheive anywhere close to 6.4GBps on RIO running at speeds less than 1GHz and 16bit data paths. At 800-950MHz speeds it needs to be 32bits because if the memory controller is outside the processor die and bandwidth is shared on that bus now with memory/PCI/AGP and other peripherals, ~6.4GBp will still be pretty sufficient. If maxed out, PCI-X takes 1GBps, AGP 8X 2.1GBps, memory will still have an open 2.7-3.2GBps.
My predictions for the 15th?
GPUL will be dual core, 16 stage pipeline for the FXUs and 21 stages for the FPUs, 512KB L2, no memory controller, HT bus running ay half the core speed, with a seperate VMX unit (with exclusive registers)in each processor core. Speeds? just under 2GHz.
<strong>...16 stage pipeline for the FXUs and 21 stages for the FPUs...</strong><hr></blockquote>
Pretty long pipelines, no? We'll be gettinginto P4 territory!?
How many stages on Power4 and current G4s?
<strong>would they still have to have DDR 400 or DDR II if only 3.2GB/s memory bandwidth?</strong><hr></blockquote>
Whats about "Dual-Channel" DDR-RAM?
The time before that was thread by Kormac76 that seemd to confirm every possible handheld device, and a slimline Vio-esque laptop in the future would be comming solely from Apple.
All I have to say on all this (again) is dont get your hopes up too high.
After both of these shows people were screaming all over the internet saying things like "where's my Dual 1GHz+ G4+'s, w/ firewire-2, USB 2.0, and DDR?"
As if Apple had told them that was what to expect.
Until Apple announces (or actually ship's) something. I wouldn't count on any of this stuff being in any future Mac's.
I hate to burst your bubble, or slow/change the momentum of this thread, but I thought the words of a realist were overdue in here.
<strong>
Until Apple announces (or actually ship's) something. I wouldn't count on any of this stuff being in any future Mac's.
</strong><hr></blockquote>
Good advice. A couple things make this thread a little different. The chip is real and will be the topic of a presentation on October 15th. We are in the single digits now, counting down to that event, and I guess we like to speculate about details of this 64-bit wonder.
You are correct. We can't be absolutely sure that Apple will use it in a Macintosh. However, even here there is more than usual hard evidence that indicates it is highly likely. For one, consider Apple's purchase of several high end video and special effects software companies. Applications like this need workstation class hardware, and this chip is the only known PPC candidate to give such performance to the Mac. Apple is not in the habit of buying software companies to let them run the products on competing hardware.
<strong>first of all motorola will make it and ibm will manufacture it. ibm will do mass production. it will come out in 5 months. trust me I know cause my friend wroks for apple.</strong><hr></blockquote>
I realize that past experience teaches people to be skeptical when confronted with such statements, but Yoyo's assertion is actually wholly accurate in this instance. I can confirm this, as Molly, my tapeworm, has three million offspring living in Steve Jobs' intestine. More surprisingly, Molly tells me that Jobs' has been eating a lot of Taco Bell lately and has taken to washing it down with beverages from the reinvigorated Fanta soft drink line, particularly the Pineapple flavor. Of course, Steve's various bodily parasites like to gab, and a Herpes virus told one of Molly's larvae that Stevey's newfound proclivity for Fanta is, in fact, because Steve "wanna wanna" real bad.
<strong>
After looking at alot of information, I have reversed my opinion the ApplePi is based on RapidIO but rather it is a version of Hyper Transport. I don't see how they can acheive anywhere close to 6.4GBps on RIO running at speeds less than 1GHz and 16bit data paths. At 800-950MHz speeds it needs to be 32bits because if the memory controller is outside the processor die and bandwidth is shared on that bus now with memory/PCI/AGP and other peripherals, ~6.4GBp will still be pretty sufficient. If maxed out, PCI-X takes 1GBps, AGP 8X 2.1GBps, memory will still have an open 2.7-3.2GBps.
My predictions for the 15th?
GPUL will be dual core, 16 stage pipeline for the FXUs and 21 stages for the FPUs, 512KB L2, no memory controller, HT bus running ay half the core speed, with a seperate VMX unit (with exclusive registers)in each processor core. Speeds? just under 2GHz.</strong><hr></blockquote>
I'm not sure why you say that the processor's bandwidth needs to be shared with all the I/O ports...? The ApplePi bus will likely connect the processor to the memory controller, and this will be integral with the I/O chipset or connected to it via another point-to-point link. I'd also expect that in an SMP machine (err, I mean multi-chip not just a single multi-core chip) the memory chipset would support one point-to-point link to each processor die. Memory bus snooping would need to happen in the chipset, or the memory controller would put all transactions on all the interconnects so that processors can snoop. Each processor die would then have a 6.4 GB/sec connection to the memory controller, and the I/O system would have its own connection(s). This is the same as the arrangement in the current DDR PowerMacs. Apple can then do whatever it wants in terms of the actual memory implementation -- DDR333/400, DDR-II, dual channel, etc. Heck, they could just put a HyperTransport connection to the video chipset (instead of AGP) and use its VRAM! 128+ MB of 20 GB/sec memory is nothing to sneeze at.
<strong>
I realize that past experience teaches people to be skeptical when confronted with such statements, but Yoyo's assertion is actually wholly accurate in this instance. I can confirm this, as Molly, my tapeworm, has three million offspring living in Steve Jobs' intestine. More surprisingly, Molly tells me that Jobs' has been eating a lot of Taco Bell lately and has taken to washing it down with beverages from the reinvigorated Fanta soft drink line, particularly the Pineapple flavor. Of course, Steve's various bodily parasites like to gab, and a Herpes virus told one of Molly's larvae that Stevey's newfound proclivity for Fanta is, in fact, because Steve "wanna wanna" real bad.</strong><hr></blockquote>
Molly's a BITCH! She told me I was her only bowel....