Power4 has a rather long pipeline if I understand it correctly, and some have speculated that PPC 970 will have an even longer one. Since it seems that 970 will be single core, does anyone know if IBM has dabbled int the arts of hyperthreading to increase performance?
Too lazy to dig this up myself, but I recall this being discussed in an Ars thread in Mac Achaia. I think there was a strong expectation that the answer is "Yes".
IBM were planning multithreading for the POWER5 so it likely will come down the line but I don't believe it will be included in this chip at the outset.
Reading THE press release made the hairs on my neck bristle.
Nice catch folks.
"Can you tell I'm talking about stuff that I know very little about?"
I'll give you points for trying
The next 9 months of my life can't go fast enough.
Roll on New York 2003. My cheque book will be ready and waiting. This is the chip (bar catastrophe...) I've been waiting for.
Equivalent of a 4 gig G4 just on mhz per mhz comparisons...then you've got bandwidth improvements ala massive.
Tech' question: 'Won't VMX perform much faster at a higher mhz? ie VMX at 1.8 compared to altivec at 1.25? And it won't be as constrained by bandwidth as the current machines are?'
Altivec stuff should really fly on the GPUL.
LEMON BON BON
PS. New case...there's gotta be a new case for these machines...cube case with 'an excitement on'. Pictures that in head said he.
IBM is definitely including multithreading with the POWER5 and I assume that is what Mr NSX refers to. It is really just a matter of will it also come with the GP-UL. My guess would be not initially but down the track it will.
52million transistors. Definitely single core. but my prediction that it has a bus that runs at 2:1 ratio of system performance was confirmed in the IBM press release. Nice. 900MHz system bus. Also, the press release does not give a specific time for release (not even an approximation) it simply states, "IBM plans to make the PowerPC 970 chip available next year."
IBM today announced a newly-developed, high-performance PowerPC microprocessor for use in a variety of applications, including desktops, workstations, servers and communications products.
The new chip, called the IBM PowerPC 970, is derived from IBM?s award-winning POWER4 server processor to provide high performance and additional function for users. As the first in a new family of high-end PowerPC processors, the chip is designed for initial speeds of up to 1.8 gigahertz, manipulating data in larger, 64-bit chunks and accelerating compute-intensive workloads like multimedia and graphics through specialized circuitry known as a single instruction multiple data (SIMD) unit.
IBM plans to build the chip in its new state-of-the-art 300mm manufacturing facility here using leading-edge manufacturing technologies. IBM plans to pack performance and new features into the chip using ultra-thin 0.13-micron circuitry (nearly 800 times thinner than a human hair), constructed of copper wiring and about 52 million transistors based on IBM?s efficient silicon-on-insulator (SOI) technology. Additional details on the PowerPC 970 are to be disclosed by IBM this week in a paper presented at Microprocessor Forum, a chip design conference organized by industry analyst firm In-Stat/MDR.
"IBM's new PowerPC 970 64-bit chip is all about bringing high-end server processing power to the desktop, low-end server and pervasive space," said Michel Mayer, general manager, IBM Microelectronics Division. "IBM is committed to helping more customers put our expertise in advanced chip design and manufacturing technology to work for them."
The chip incorporates an innovative communications link, or "bus," specially developed to speed information between the processor and memory. Running at a speed of up to 900 megahertz, the bus can deliver information to the processor at up to 6.4 gigabytes per second, to help ensure that the high-performance processor is fed data at sufficient speeds.
While supporting 64-bit computing for emerging applications, the PowerPC 970 also provides native support for traditional 32-bit applications, which can help preserve users? and developers? software investments. The design also supports symmetric multi-processing (SMP), allowing systems to be created that link multiple processors to work in tandem for additional processing power.
IBM plans to make the PowerPC 970 chip available next year.
So it's .13 with 52 million transistors with a 900 MHZ bus between the processor and memory as stated by Outsider. No mention of RapidIO or HyperTransport or Apple PI, just "an innovative communications link, or "bus," specially developed to speed information between the processor and memory."
Maximum speed is 800MHz. PowerPC 970 runs at minimum 900MHz. But RapidIO can run at over 1GHz. Some food for thought.</strong><hr></blockquote>
Outsider...
"Running at a speed of up to 900 megahertz, the bus can deliver information to the processor at up to 6.4 gigabytes per second, to help ensure that the high-performance processor is fed data at sufficient speeds."
"HyperTransportÂ?Â* technology devices are designed to operate at multiple clock speeds from 200MHz up to 800MHz, and utilizes double data rate technology transferring two bits of data per clock cycle, for an effective transfer rate of up to 1,600Mb/sec in each direction. Since transfers can occur in both directions simultaneously, an aggregate transfer rate of 6.4 Gigabytes per second in a 16 bit HyperTransportÂ?Â* I/O Link and an aggregate transfer rate of 12.8 Gigabytes per second in a 32-bit HyperTransportÂ?Â* I/O Link can be achieved. To allow for system design optimization, the clocks of the receive and transmit links may be set at different rates.
"
The IBM press release says up to 900MHz indeed, but this is because of the initial speed of 900MHz is a multiple of the top speed of the chip 1.8GHz. Maybe this is an indication that they will be offered at lower speeds also. Perhaps 1.6, 1.7, 1.8GHz with 800, 850, and 900MHz bus speeds respectively. This is an assumption.
The IBM 970 may be the beginning of Apple's shift to IBM as its primary supplier of processors. IBM could develop lower performance, lower power versions, to replace G4s and G3s. Notice the number, 970. It is rather high up in 900 block of numbers, leaving room below it for lower performing chips.
". . . As the first in a new family of high-end PowerPC processors, the chip is designed for initial speeds of up to 1.8 gigahertz . . ."
<a href="http://news.google.com/news?hl=en&q=ibm+970"; target="_blank">Here</a> is a good roundup of many of the latest articles. They are all based upon the same press release, but each offers a slightly different set of predictions based upon the information.
"However, Microprocessor Report editor in chief Peter Glaskowsky told Macworld in August: ?My understanding is that the G5 processor will appear in Macs in due course, and that Motorola intends to support and extend this product line as long as Apple remains in business.?"
"However, Microprocessor Report editor in chief Peter Glaskowsky told Macworld in August: ?My understanding is that the G5 processor will appear in Macs in due course, and that Motorola intends to support and extend this product line as long as Apple remains in business.?"</strong><hr></blockquote>
We're waiting and waiting and waiting. Hopefully, the wait will be over in Jan.
"However, Microprocessor Report editor in chief Peter Glaskowsky told Macworld in August: ?My understanding is that the G5 processor will appear in Macs in due course, and that Motorola intends to support and extend this product line as long as Apple remains in business.?"</strong><hr></blockquote>
Did I miss something? The text you quote isn't in the article you link to.
The new IBM press release tells us 52 million transistors, 0.13 micron, 1.8 GHz, and 900 MHz bus. Interesting...
So a 900 MHz bus capable of 6.4 GB/sec; that's 56.88 bits/clock which means its either 64 bits wide single pumped, 32 bits wide double pumped, or 16 bits wide quad pumped. I suppose they could have pushed the HyperTransport spec, but I'm doubting it. Its also quite a bump to the current state of RapidIO so I'm thinking its a new proprietary bus design -- perhaps ApplePi? If the goal is to make it a dedicated processor interconnect and leave any bridging and IO to the chipset then this doesn't really matter, indeed, it is the same as Intel's approach.
0.13 micron copper SOI, 1.8 GHz and only 52 million transistors is pretty conservative compared to AMD & Intel's offerings so this thing may have some real legs (hence their mention of future designs). It probably SPECs pretty well too. Another thing to consider -- performance typically scales worse and worse as you push the clock rate higher and higher. Going from a 1GHz processor to a 2GHz processor gives you more real performance than the leap from 2GHz to 3GHz, mostly due to outstripping the speed of memory and IO. This makes it likely that the PowerPC leaping from 1.25GHz to 1.8GHz will be a bigger improvement than Intel tacking on an extra GHz or two above the 2GHz mark, especially with this new 6.4 GB/sec FSB.
I can't wait to hear more details (and hopefully some SPECmark claims) tomorrow. This thing is about 20% smaller than the PIV and has the potential to be a better performer. Followup chips which include multiple cores, hyperthreading, higher clock rates could mean a lot of fun in Apple's future.
I don't think the Motorola G5 in its current form will go into Macs.
The SNDF doco released by Motorola puts the G4+ core as the high-end core.
In the next breath, Motorola is "committed to Rapid-I/O being the interconnect architecture in all future products".
Is a G4 core with Rapid I/O (and possibly OCEAN) a G5? It's usually the core that determines the CPU genetation. At least, every x86 CPU has worked that way.
Comments
[ 10-14-2002: Message edited by: Telomar ]</p>
Nice catch folks.
"Can you tell I'm talking about stuff that I know very little about?"
I'll give you points for trying
The next 9 months of my life can't go fast enough.
Roll on New York 2003. My cheque book will be ready and waiting. This is the chip (bar catastrophe...) I've been waiting for.
Equivalent of a 4 gig G4 just on mhz per mhz comparisons...then you've got bandwidth improvements ala massive.
Tech' question: 'Won't VMX perform much faster at a higher mhz? ie VMX at 1.8 compared to altivec at 1.25? And it won't be as constrained by bandwidth as the current machines are?'
Altivec stuff should really fly on the GPUL.
LEMON BON BON
PS. New case...there's gotta be a new case for these machines...cube case with 'an excitement on'. Pictures that in head said he.
[ 10-14-2002: Message edited by: Lemon Bon Bon ]</p>
Here's the url about hyperthreading: <a href="http://arstechnica.infopop.net/OpenTopic/page?a=tpc&s=50009562&f=8300945231&m=2060912535"; target="_blank">Ars hyperthreading, um, thread</a>.
Mr NSX is by all accounts a real insider: he works for ATi IIRC.
IBM unveils new 64-bit PowerPC® microprocessor
East Fishkill, NY - October 14, 2002
IBM today announced a newly-developed, high-performance PowerPC microprocessor for use in a variety of applications, including desktops, workstations, servers and communications products.
The new chip, called the IBM PowerPC 970, is derived from IBM?s award-winning POWER4 server processor to provide high performance and additional function for users. As the first in a new family of high-end PowerPC processors, the chip is designed for initial speeds of up to 1.8 gigahertz, manipulating data in larger, 64-bit chunks and accelerating compute-intensive workloads like multimedia and graphics through specialized circuitry known as a single instruction multiple data (SIMD) unit.
IBM plans to build the chip in its new state-of-the-art 300mm manufacturing facility here using leading-edge manufacturing technologies. IBM plans to pack performance and new features into the chip using ultra-thin 0.13-micron circuitry (nearly 800 times thinner than a human hair), constructed of copper wiring and about 52 million transistors based on IBM?s efficient silicon-on-insulator (SOI) technology. Additional details on the PowerPC 970 are to be disclosed by IBM this week in a paper presented at Microprocessor Forum, a chip design conference organized by industry analyst firm In-Stat/MDR.
"IBM's new PowerPC 970 64-bit chip is all about bringing high-end server processing power to the desktop, low-end server and pervasive space," said Michel Mayer, general manager, IBM Microelectronics Division. "IBM is committed to helping more customers put our expertise in advanced chip design and manufacturing technology to work for them."
The chip incorporates an innovative communications link, or "bus," specially developed to speed information between the processor and memory. Running at a speed of up to 900 megahertz, the bus can deliver information to the processor at up to 6.4 gigabytes per second, to help ensure that the high-performance processor is fed data at sufficient speeds.
While supporting 64-bit computing for emerging applications, the PowerPC 970 also provides native support for traditional 32-bit applications, which can help preserve users? and developers? software investments. The design also supports symmetric multi-processing (SMP), allowing systems to be created that link multiple processors to work in tandem for additional processing power.
IBM plans to make the PowerPC 970 chip available next year.
So it's .13 with 52 million transistors with a 900 MHZ bus between the processor and memory as stated by Outsider. No mention of RapidIO or HyperTransport or Apple PI, just "an innovative communications link, or "bus," specially developed to speed information between the processor and memory."
[ 10-14-2002: Message edited by: CodeWarrior ]</p>
Maximum speed is 800MHz. PowerPC 970 runs at minimum 900MHz. But RapidIO can run at over 1GHz. Some food for thought.
<strong>I think I reverse my opinion on ApplePi using HyperTransport as the basis of the bus. Look at question 11 on this page: <a href="http://hypertransport.org/faqs.html"; target="_blank">http://hypertransport.org/faqs.html</a>;
Maximum speed is 800MHz. PowerPC 970 runs at minimum 900MHz. But RapidIO can run at over 1GHz. Some food for thought.</strong><hr></blockquote>
Outsider...
"Running at a speed of up to 900 megahertz, the bus can deliver information to the processor at up to 6.4 gigabytes per second, to help ensure that the high-performance processor is fed data at sufficient speeds."
Dave
"HyperTransportÂ?Â* technology devices are designed to operate at multiple clock speeds from 200MHz up to 800MHz, and utilizes double data rate technology transferring two bits of data per clock cycle, for an effective transfer rate of up to 1,600Mb/sec in each direction. Since transfers can occur in both directions simultaneously, an aggregate transfer rate of 6.4 Gigabytes per second in a 16 bit HyperTransportÂ?Â* I/O Link and an aggregate transfer rate of 12.8 Gigabytes per second in a 32-bit HyperTransportÂ?Â* I/O Link can be achieved. To allow for system design optimization, the clocks of the receive and transmit links may be set at different rates.
"
The IBM press release says up to 900MHz indeed, but this is because of the initial speed of 900MHz is a multiple of the top speed of the chip 1.8GHz. Maybe this is an indication that they will be offered at lower speeds also. Perhaps 1.6, 1.7, 1.8GHz with 800, 850, and 900MHz bus speeds respectively. This is an assumption.
". . . As the first in a new family of high-end PowerPC processors, the chip is designed for initial speeds of up to 1.8 gigahertz . . ."
[ 10-14-2002: Message edited by: snoopy ]</p>
<strong>
Sure -- the difference is that the people who were claiming the G5 was coming out had absolutely no clue what they were talking about.
The GP-UL, on the other hand, is very real.</strong><hr></blockquote>
Peter Glaskowsky of Microprocessor Reports says the G5 is coming. Check this link...
<a href="http://www.macworld.co.uk/news/top_news_item.cfm?NewsID=5400"; target="_blank">http://www.macworld.co.uk/news/top_news_item.cfm?NewsID=5400</a>;
Some text from the link:
"However, Microprocessor Report editor in chief Peter Glaskowsky told Macworld in August: ?My understanding is that the G5 processor will appear in Macs in due course, and that Motorola intends to support and extend this product line as long as Apple remains in business.?"
<strong>
"However, Microprocessor Report editor in chief Peter Glaskowsky told Macworld in August: ?My understanding is that the G5 processor will appear in Macs in due course, and that Motorola intends to support and extend this product line as long as Apple remains in business.?"</strong><hr></blockquote>
We're waiting and waiting and waiting. Hopefully, the wait will be over in Jan.
<strong>
Peter Glaskowsky of Microprocessor Reports says the G5 is coming. Check this link...
<a href="http://www.macworld.co.uk/news/top_news_item.cfm?NewsID=5400"; target="_blank">http://www.macworld.co.uk/news/top_news_item.cfm?NewsID=5400</a>;
Some text from the link:
"However, Microprocessor Report editor in chief Peter Glaskowsky told Macworld in August: ?My understanding is that the G5 processor will appear in Macs in due course, and that Motorola intends to support and extend this product line as long as Apple remains in business.?"</strong><hr></blockquote>
Did I miss something? The text you quote isn't in the article you link to.
The new IBM press release tells us 52 million transistors, 0.13 micron, 1.8 GHz, and 900 MHz bus. Interesting...
So a 900 MHz bus capable of 6.4 GB/sec; that's 56.88 bits/clock which means its either 64 bits wide single pumped, 32 bits wide double pumped, or 16 bits wide quad pumped. I suppose they could have pushed the HyperTransport spec, but I'm doubting it. Its also quite a bump to the current state of RapidIO so I'm thinking its a new proprietary bus design -- perhaps ApplePi? If the goal is to make it a dedicated processor interconnect and leave any bridging and IO to the chipset then this doesn't really matter, indeed, it is the same as Intel's approach.
0.13 micron copper SOI, 1.8 GHz and only 52 million transistors is pretty conservative compared to AMD & Intel's offerings so this thing may have some real legs (hence their mention of future designs). It probably SPECs pretty well too. Another thing to consider -- performance typically scales worse and worse as you push the clock rate higher and higher. Going from a 1GHz processor to a 2GHz processor gives you more real performance than the leap from 2GHz to 3GHz, mostly due to outstripping the speed of memory and IO. This makes it likely that the PowerPC leaping from 1.25GHz to 1.8GHz will be a bigger improvement than Intel tacking on an extra GHz or two above the 2GHz mark, especially with this new 6.4 GB/sec FSB.
I can't wait to hear more details (and hopefully some SPECmark claims) tomorrow. This thing is about 20% smaller than the PIV and has the potential to be a better performer. Followup chips which include multiple cores, hyperthreading, higher clock rates could mean a lot of fun in Apple's future.
<strong>
Did I miss something? The text you quote isn't in the article you link to.
</strong><hr></blockquote>
Programmer,
Just tried it. It's at the bottom of the page.
The SNDF doco released by Motorola puts the G4+ core as the high-end core.
In the next breath, Motorola is "committed to Rapid-I/O being the interconnect architecture in all future products".
Is a G4 core with Rapid I/O (and possibly OCEAN) a G5? It's usually the core that determines the CPU genetation. At least, every x86 CPU has worked that way.
January 2002: 180nm SOI G4+
March 2002: 130nm SOI G3
January 2003: 130nm SOI G4+
Mid/Late 2003: 130nm PowerPC 970
Late 2003/Early 2004: 90nm PowerPC 970
2004 at the earliest: G4++ with Rapid I/O
Barto