4MB cache? Wow. I wonder if it really makes a meaningful difference for anything outside of scientific or server benchmarks. Up until then, 2MB per core is something you couldn't get outside of a Xeon MP or some RISC systems.
4MB cache? Wow. I wonder if it really makes a meaningful difference for anything outside of scientific benchmarks. 2MB per core was something you couldn't get outside of a Xeon MP or some RISC systems.
Sure. It makes up for memory bandwidth, and latency.
Sure. It makes up for memory bandwidth, and latency.
The reason I said that is that I've seen a few tests that showed that going from 1MB to 2MB cache on (I think Dothan generation) Intel mobile chips yeilded little speed difference, so it would seem that 2MB to 4MB (1 to 2MB per core) would be insignificant.
The reason I said that is that I've seen a few tests that showed that going from 1MB to 2MB cache on Intel chips yeilded little speed difference, so it would seem that 2MB to 4MB would be insignificant.
I don't know what those tests were, or with which chips, but it makes a rather large difference.
The main speed feature differences between the chips are cache size (1M vs. 2M) and a very slight clock difference, the Celeron even has a slower FSB. If more than 1M cache makes a difference on memory bandwidth limited chips, then it should show in those tests.
If you've seen something else that shows otherwise, I'd like to see it.
"There's also the possibility that the notebooks will be made available in fashionable hues, these people have said."
It sounds as though the only hue right now that would actually sell is black!, the ipods have demonstrated that this colour might be more popular than white.
I still think that a Macbook should be available in a larger screen size than 13.3" and still not cannibilize the Pro line?. I think apple needs a "consumer" 15" machine in this quadrant.
"There's also the possibility that the notebooks will be made available in fashionable hues, these people have said."
It sounds as though the only hue right now that would actually sell is black!, the ipods have demonstrated that this colour might be more popular than white.
I still think that a Macbook should be available in a larger screen size than 13.3" and still not cannibilize the Pro line?. I think apple needs a "consumer" 15" machine in this quadrant.
Maybe when the MBP's get the upgrade to meroms. Until then there is not enough difference between the two to even consider it.
The main speed feature differences between the chips are cache size (1M vs. 2M) and a very slight clock difference, the Celeron even has a slower FSB. If more than 1M cache makes a difference on memory bandwidth limited chips, then it should show in those tests.
If you've seen something else that shows otherwise, I'd like to see it.
That doesn't show very much. Also, different cpu's take advantage of cache differently. I'm also not so convinced that that machine is eht best design out there.
I'm surprised that you haven't read the many articles about why cache is so important, and how Intel uses it to help make up for it's low memory bandwidth.
The new G5 uses its 1MB cache to make up for its slower speed, and shared memory bus. That's why the dual core 2.5GHz model can actually score higher on many tests than the older dual chip 2.7GHz model.
I usually don't like looking up old articles, but if I do come across one, I'll post it.
The main speed feature differences between the chips are cache size (1M vs. 2M) and a very slight clock difference, the Celeron even has a slower FSB. If more than 1M cache makes a difference on memory bandwidth limited chips, then it should show in those tests.
If you've seen something else that shows otherwise, I'd like to see it.
How useful an extra 1 MB cache is depends greatly on what software you are running. It is easy to write software that performs no better with double the cache, and it is easy to write software the performs enormously better with double the cache.
The new G5 uses its 1MB cache to make up for its slower speed, and shared memory bus. That's why the dual core 2.5GHz model can actually score higher on many tests than the older dual chip 2.7GHz model.
That's not that much of a boost, and that is from 512k to 1M. I suspect that the benefit of jumping from 1M to 2M would be even less.
I know cache is important, but as with anything else, there is a point of diminishing returns. Save for certain RISC (Alpha, PA, SPARC and such) or server systems, I haven't seen much of backed-up claims of actual benefits of going for more than 1M per chip, or core.
That's not much of a boost, and that is from 512k to 1M. I suspect that the benefit of jumping from 1M to 2M would be even less.
That's a pretty big boost. I don't know what you are expecting. Going from 512K to 1MB, and getting 10% is pretty joyous. If they went to 2MB, it could have been about 20%.
That would bring the G5 up to the level of the Opteron, and slightly ahead of the Xeon.
4MB could add another 10 to 15% to that score.
Those are pretty big numbers.
There is a reason why big iron cpu's have massive caches up to 64MB's in size.
Don't forget that the Power also has the L3 cache that was dropped on the G5 because of cost. That would add another 10 to 20% in performance.
The greater the latency of the memory bus, the more effective the cache is also. with DDR2, it makes more of a difference that it would have with the older DDR 1 that the test machine had ? less latency.
What Programmer said is also correct. That's why that test you showed didn't seem useful to me.
What Programmer said is also correct. That's why that test you showed didn't seem useful to me.
That's the thing, it was with actual software that is in use in typical consumer systems, not some custom tweaked code with massive data sets, which is what the "big iron" stuff gets tangled with.
As you say, there is a cost to it as well, increasing the die size has a cost attached, and adding maybe 30% more total transistors for 10% faster speed doesn't sound like a good use of die space and cost to me. For the Xeon MP, the extra cache it had did make a difference, but that was with the restrictive shared bus sharing four hyperthreaded processors, two restrictions the Merom won't face in typical use.
That's the thing, it was with actual software that is in use, not some custom tweaked code with massive data sets, which is what the "big iron" stuff gets tangled with. As you say, there is a cost to it as well, increasing the die size has a cost attached, and adding maybe 30% more total transistors for 10% faster speed doesn't sound like a good use of die space and cost to me.
Maybe not to you, but it does to most cpu designers.
Maybe not to you, but it does to most cpu designers.
Maybe. Still, going from 512 to 1M is a different thing than going from 1M to 2M. I thought the introduction of the Intel Extreme Edition was another example that showed that going past 1M had negligible benefit for off-the-shelf apps on the x86 architecture.
Maybe. Still, going from 512 to 1M is a different thing than going from 1M to 2M. I thought the introduction of the Intel Extreme Edition was another example that showed that going past 1M had negligible benefit for off-the-shelf apps on the x86 architecture.
Going from 1MB to 2 MB, and from 2MB to 4MB gives about the same advantage as going from 512K to 1MB. But, you notice that you have to double each time.
The advantage of cache is that it uses very little power, and therefore gives off less heat than increased numeric circuits on the cpu itself would.
That's why, for example, a 1.83GHz Yonah with 4MB cache would at least equal the performance of a 2MB cache 2GHz chip. It's one of the reasons why Merom will be 20% better at the same freq., while using the same power.
And, cache is useful far more often then it isn't. This has been understood since the early '80's, when cache first appeared.
And, cache is useful far more often then it isn't. This has been understood since the early '80's, when cache first appeared.
I have never said to eliminate the cache, just that there is a diminishing return when going beyond a certain point. If you can show me examples of an off-the-shelf desktop app on an x86 chip benefits more than a couple percent when going from 1M to 2M, I would like to see it, but I have not seen it happen.
I have never said to eliminate the cache, just that there is a diminishing return when going beyond a certain point.. If you can show me examples of an off-the-shelf desktop app on an x86 chip benefits more than a couple percent when going from 1M to 2M, I would like to see it, but I have not seen it happen.
Jeff, they generally don't do those kinds of tests. They check different cpus. If the cache is different, there is usually some other difference as well. Just look around the web for articles about cache and you will see for yourself.
With many cpu designs the cache doesn't even begin to have a significent advantage until a lot more is added. Check out the Itanium, for example. The huge cache is credited with a good deal of the performance, particularly as the memory bus is slow, with lots of latency.
Comments
Originally posted by manjaap
I do not give a damn about the price. just give me my macbook Steve
If price is no obstacle, get a MBP.
There are two levels of Merom's, the T5000 family, with 2MB L2 cache, and the T7000, with 4MB l2 cache.
More info is here.
http://www.tgdaily.com/2006/05/07/in...e_2_duo_brand/
Originally posted by melgross
Maybe this will give some help to the price question. (Or maybe not).
There are two levels of Merom's, the T5000 family, with 2MB L2 cache, and the T7000, with 4MB l2 cache.
More info is here.
http://www.tgdaily.com/2006/05/07/in...e_2_duo_brand/
4MB cache? Wow. I wonder if it really makes a meaningful difference for anything outside of scientific or server benchmarks. Up until then, 2MB per core is something you couldn't get outside of a Xeon MP or some RISC systems.
Originally posted by JeffDM
4MB cache? Wow. I wonder if it really makes a meaningful difference for anything outside of scientific benchmarks. 2MB per core was something you couldn't get outside of a Xeon MP or some RISC systems.
Sure. It makes up for memory bandwidth, and latency.
Originally posted by melgross
Sure. It makes up for memory bandwidth, and latency.
The reason I said that is that I've seen a few tests that showed that going from 1MB to 2MB cache on (I think Dothan generation) Intel mobile chips yeilded little speed difference, so it would seem that 2MB to 4MB (1 to 2MB per core) would be insignificant.
Originally posted by JeffDM
The reason I said that is that I've seen a few tests that showed that going from 1MB to 2MB cache on Intel chips yeilded little speed difference, so it would seem that 2MB to 4MB would be insignificant.
I don't know what those tests were, or with which chips, but it makes a rather large difference.
Originally posted by melgross
I don't know what those tests were, or with which chips, but it makes a rather large difference.
These tests showed me that the difference is insignificant:
Comparison
The main speed feature differences between the chips are cache size (1M vs. 2M) and a very slight clock difference, the Celeron even has a slower FSB. If more than 1M cache makes a difference on memory bandwidth limited chips, then it should show in those tests.
If you've seen something else that shows otherwise, I'd like to see it.
It sounds as though the only hue right now that would actually sell is black!, the ipods have demonstrated that this colour might be more popular than white.
I still think that a Macbook should be available in a larger screen size than 13.3" and still not cannibilize the Pro line?. I think apple needs a "consumer" 15" machine in this quadrant.
Originally posted by hasapi
"There's also the possibility that the notebooks will be made available in fashionable hues, these people have said."
It sounds as though the only hue right now that would actually sell is black!, the ipods have demonstrated that this colour might be more popular than white.
I still think that a Macbook should be available in a larger screen size than 13.3" and still not cannibilize the Pro line?. I think apple needs a "consumer" 15" machine in this quadrant.
Maybe when the MBP's get the upgrade to meroms. Until then there is not enough difference between the two to even consider it.
Originally posted by JeffDM
These tests showed me that the difference is insignificant:
Comparison
The main speed feature differences between the chips are cache size (1M vs. 2M) and a very slight clock difference, the Celeron even has a slower FSB. If more than 1M cache makes a difference on memory bandwidth limited chips, then it should show in those tests.
If you've seen something else that shows otherwise, I'd like to see it.
That doesn't show very much. Also, different cpu's take advantage of cache differently. I'm also not so convinced that that machine is eht best design out there.
I'm surprised that you haven't read the many articles about why cache is so important, and how Intel uses it to help make up for it's low memory bandwidth.
The new G5 uses its 1MB cache to make up for its slower speed, and shared memory bus. That's why the dual core 2.5GHz model can actually score higher on many tests than the older dual chip 2.7GHz model.
I usually don't like looking up old articles, but if I do come across one, I'll post it.
Originally posted by JeffDM
These tests showed me that the difference is insignificant:
Comparison
The main speed feature differences between the chips are cache size (1M vs. 2M) and a very slight clock difference, the Celeron even has a slower FSB. If more than 1M cache makes a difference on memory bandwidth limited chips, then it should show in those tests.
If you've seen something else that shows otherwise, I'd like to see it.
How useful an extra 1 MB cache is depends greatly on what software you are running. It is easy to write software that performs no better with double the cache, and it is easy to write software the performs enormously better with double the cache.
Originally posted by melgross
The new G5 uses its 1MB cache to make up for its slower speed, and shared memory bus. That's why the dual core 2.5GHz model can actually score higher on many tests than the older dual chip 2.7GHz model.
That's not that much of a boost, and that is from 512k to 1M. I suspect that the benefit of jumping from 1M to 2M would be even less.
I know cache is important, but as with anything else, there is a point of diminishing returns. Save for certain RISC (Alpha, PA, SPARC and such) or server systems, I haven't seen much of backed-up claims of actual benefits of going for more than 1M per chip, or core.
Originally posted by JeffDM
That's not much of a boost, and that is from 512k to 1M. I suspect that the benefit of jumping from 1M to 2M would be even less.
That's a pretty big boost. I don't know what you are expecting. Going from 512K to 1MB, and getting 10% is pretty joyous. If they went to 2MB, it could have been about 20%.
That would bring the G5 up to the level of the Opteron, and slightly ahead of the Xeon.
4MB could add another 10 to 15% to that score.
Those are pretty big numbers.
There is a reason why big iron cpu's have massive caches up to 64MB's in size.
Don't forget that the Power also has the L3 cache that was dropped on the G5 because of cost. That would add another 10 to 20% in performance.
The greater the latency of the memory bus, the more effective the cache is also. with DDR2, it makes more of a difference that it would have with the older DDR 1 that the test machine had ? less latency.
What Programmer said is also correct. That's why that test you showed didn't seem useful to me.
Originally posted by melgross
What Programmer said is also correct. That's why that test you showed didn't seem useful to me.
That's the thing, it was with actual software that is in use in typical consumer systems, not some custom tweaked code with massive data sets, which is what the "big iron" stuff gets tangled with.
As you say, there is a cost to it as well, increasing the die size has a cost attached, and adding maybe 30% more total transistors for 10% faster speed doesn't sound like a good use of die space and cost to me. For the Xeon MP, the extra cache it had did make a difference, but that was with the restrictive shared bus sharing four hyperthreaded processors, two restrictions the Merom won't face in typical use.
Originally posted by JeffDM
That's the thing, it was with actual software that is in use, not some custom tweaked code with massive data sets, which is what the "big iron" stuff gets tangled with. As you say, there is a cost to it as well, increasing the die size has a cost attached, and adding maybe 30% more total transistors for 10% faster speed doesn't sound like a good use of die space and cost to me.
Maybe not to you, but it does to most cpu designers.
Originally posted by melgross
Maybe not to you, but it does to most cpu designers.
Maybe. Still, going from 512 to 1M is a different thing than going from 1M to 2M. I thought the introduction of the Intel Extreme Edition was another example that showed that going past 1M had negligible benefit for off-the-shelf apps on the x86 architecture.
Originally posted by JeffDM
Maybe. Still, going from 512 to 1M is a different thing than going from 1M to 2M. I thought the introduction of the Intel Extreme Edition was another example that showed that going past 1M had negligible benefit for off-the-shelf apps on the x86 architecture.
Going from 1MB to 2 MB, and from 2MB to 4MB gives about the same advantage as going from 512K to 1MB. But, you notice that you have to double each time.
The advantage of cache is that it uses very little power, and therefore gives off less heat than increased numeric circuits on the cpu itself would.
That's why, for example, a 1.83GHz Yonah with 4MB cache would at least equal the performance of a 2MB cache 2GHz chip. It's one of the reasons why Merom will be 20% better at the same freq., while using the same power.
And, cache is useful far more often then it isn't. This has been understood since the early '80's, when cache first appeared.
Originally posted by melgross
And, cache is useful far more often then it isn't. This has been understood since the early '80's, when cache first appeared.
I have never said to eliminate the cache, just that there is a diminishing return when going beyond a certain point. If you can show me examples of an off-the-shelf desktop app on an x86 chip benefits more than a couple percent when going from 1M to 2M, I would like to see it, but I have not seen it happen.
Originally posted by JeffDM
I have never said to eliminate the cache, just that there is a diminishing return when going beyond a certain point.. If you can show me examples of an off-the-shelf desktop app on an x86 chip benefits more than a couple percent when going from 1M to 2M, I would like to see it, but I have not seen it happen.
Jeff, they generally don't do those kinds of tests. They check different cpus. If the cache is different, there is usually some other difference as well. Just look around the web for articles about cache and you will see for yourself.
With many cpu designs the cache doesn't even begin to have a significent advantage until a lot more is added. Check out the Itanium, for example. The huge cache is credited with a good deal of the performance, particularly as the memory bus is slow, with lots of latency.