<strong>Do you even know what you're talking about? There's no such thing as a 'ddr frontside bus' or whatever. 'ddr frontside buses' run at 133 mhz [so far].</strong><hr></blockquote>
There is no such thing as a DDR front side MPX bus yet. That doesn't mean Motorola doesn't have one coming in the next iteration of the G4. It would allow them to double the bandwidth without increasing the bus clock rate (which is a more difficult task since all the signals then need to run at an increased rate).
I wanted to believe the G5 was coming any day now for the better part of a year, Finally, however, I am beginning to face reality. I, like so many others, want a revolutionary turn of events for Apple. We want Apple to blow the competition away. The truth, however, is the revolution won?t happen overnight. It will be long and slow, and, while requiring a lot of work from Apple, will probably seem quite boring. The G5 will come someday, but probably not at MWNY. When it finally arrives, the surrounding competition will make it about as exciting to us as the G4 is now. <hr></blockquote>
I've lived a little over 24 hours with my new reality policy. Let me just say, reality is a harsh mistress. I'm returning to my previous methods of dealing with the situation. G5's at MWNY!
I've lived a little over 24 hours with my new reality policy. Let me just say, reality is a harsh mistress. I'm returning to my previous methods of dealing with the situation. G5's at MWNY! </strong><hr></blockquote>
Well, one thing to realize: the longer you hold out hope for the G5, the more likely it is that you will be correct.
the reason why we are all waiting for an apple g5 is because we want to beat the pc's
because most apple users are fanatics ,and i am one to.
but why are we waiting for those chips.
is it realy gonna effect the way we computer?
apple is faster anyway but pc users just dont admit it, well we know better.
i even bet that almost none of us have the fastest g4 so it is not gonna change the way you computer ,when the time is there apple will introduce an 2 ghz machine you wil be computering with an 933 so lets wait for a real anwser to this question.
Jonas, please don't post exactly the same thing to multiple threads.
Thanks.
As for a double-pumped MPX bus, I followed a link over to Ars Technica and read a few lengthy musings by BadAndy. This is what I was able to snatch from the words that went over my head:
The MaxBus is incredibly elaborate (too elaborate in his opinion). In addition to useful things like reserving (a processor tells the bus that it will receive the next X amount of information, greatly simplifying arbitration) and streaming (near 100% bus efficiency if the bus knows what's coming), it's designed to handle transactions with devices at all different levels of latency, throughput and even reliability. In other words, it's hopelessly overengineered for the work Apple requires it to do. Armed with this knowledge, and acknowledging that enough might have flown over my head that I got a few things wrong, suddenly Mot's "stalling" makes sense: It's really easy to double-pump a simple bus, but MPX is designed to have so many things going on at once, with so many caveats and conditions and contingencies (example: It can handle three failed requests per cycle with no loss of bandwidth), that getting it all to run twice as fast might be a real task. BadAndy speculates that a double-pumped MPX bus will abandon a number of the features of the original bus (hopefully the ones that Apple doesn't rely on!). But if the bus changes substantively, rather than just doing the same thing faster, then the memory controller has to be changed substantively as well, and all of a sudden there's a lot of work to do for both companies.
BTW, BadAndy and another poster determined that DDR RAM actually does help performance across MaxBus: It reduces latency. That's not an earthshaking improvement, but it certainly helps.
Again, I'm curious as to what Apple will have left to show come Macworld New York.
If ibooks are revised next week...then? Then what?
Just 'Power'mac revisions? A shipping date for Jaguar? A bump to the imac?
After a whole half a year...I find it incredulous to believe we'll only see 1.2 gig G4 macs.
A bump of 200mhz? :eek:
Maybe, like with Quartz Extreme on the OS front,
...like Blast on the science front...
...like altivec on the dvd front...
Digital Video and 3D are becoming increasingly important to apple.
If they aren't ready for true 'G5' processors with rapid io which I think most agree is the way optimistic for Macworld New York...then it's just a speed bump to Apollo in the 1 -1.2 gig or 1 - 1.4 gig range. And yes, with some form of DDR implementation.
But Mosr (now, now...stay with me a minute here...) says: new cases and 100% faster.
Where's that extra speed coming from?
A few hints say: specs will look ordinary and we'll scream blue murder... So if Apple haven't been able to get the mhz beyond 1.2 gig. Then...what?
Special hardware accleleration? A form of 'Blast' but for 3D? Didn't Raycer have some form of special 3d algorithm (spelling excuse, mental blank...) technology for reducing 3d work undertaken by 3D chip?
100% is a big leap in processing power. That's the equivalent of several 'Power'mac cpu speed bumps and a mobo revision. Where's it coming from? I don't think a cpu bump and mobo revision is going to cover that?
Apple don't control the cpu making directly. But they, to be fair, try to compensate to some degree by offering some 'gimmick', whether it's dual processor across the line or 'blast' or Quartz Extreme.
IF we do get 1.2 gig processors and a slight Mobo revision...
...then what do YOU guys think they'll have up Steve's sleeve? More reality distortion? This time, I think not...
That 100% performance increase rumour is the very reason I've been suspecting Quads are coming. IF it is true that is.
Going quad would do exactly that! Increase performance 100%. At least theoretically, and this is not an official statement so why bother with such details
If moto is coming through with a 266 MHz DDR system bus, why shouldn't apple make the absolute most of it?
It would cost, of course, but apple desperately needs as much PM performance as the can get.
<strong>That 100% performance increase rumour is the very reason I've been suspecting Quads are coming. IF it is true that is.
Going quad would do exactly that! Increase performance 100%. At least theoretically, and this is not an official statement so why bother with such details
If moto is coming through with a 266 MHz DDR system bus, why shouldn't apple make the absolute most of it?
It would cost, of course, but apple desperately needs as much PM performance as the can get.</strong><hr></blockquote>
Because putting twice as many of the most expensive, hottest, and highest pin count parts into your system will greatly impact the pricing... and you won't get anything close to a 100% performance improvement. You'd be doing well to hit 50-75%. Now, if these things were multicore, then that's another story.
<strong>That 100% performance increase rumour is the very reason I've been suspecting Quads are coming. IF it is true that is.
Going quad would do exactly that! Increase performance 100%. At least theoretically, and this is not an official statement so why bother with such details
If moto is coming through with a 266 MHz DDR system bus, why shouldn't apple make the absolute most of it?
It would cost, of course, but apple desperately needs as much PM performance as the can get.</strong><hr></blockquote>
DDR only adds 10% - 15% speed increase (mostly latency) in PC's. Apple uses a different bus achitecture. The question is "Is the Apple memory bus already giving speed increases similar to those obtained from DDR in peecees?".
Another question, What is the speed advantage of DDR cache versus DDR FSB and how does that effect overall system speed? Maybe DDR FSB is not relevant to Apple. What really needs to be done is increased bandwidth of the G4 combined with the new i/o system in the ServeX.
<strong>Just where is that rumor about 100 % speed increase from??
I have read the latest updates from MOSR, and cant find that story.. oh well. <img src="graemlins/embarrassed.gif" border="0" alt="[Embarrassed]" /> </strong><hr></blockquote>
Only place I heard of the 100% increase was at xlr8.com in a comment by Mike to another reader in a Forum.
DDR only adds 10% - 15% speed increase (mostly latency) in PC's. Apple uses a different bus achitecture. The question is "Is the Apple memory bus already giving speed increases similar to those obtained from DDR in peecees?".
...</strong><hr></blockquote>
Is this really true? I know the first gen DDR boards had about this much speed increase, but is that true now? The increased memory bandwidth is substantial, most things I have read indicate much better performance gains...any links or info would be greatly appreciated.
Is this really true? I know the first gen DDR boards had about this much speed increase, but is that true now? The increased memory bandwidth is substantial, most things I have read indicate much better performance gains...any links or info would be greatly appreciated.</strong><hr></blockquote>
Read the whole article and references- interesting info.
(edit: It's a little different for the new P4 chips)
"Is this really true? I know the first gen DDR boards had about this much speed increase, but is that true now? The increased memory bandwidth is substantial, most things I have read indicate much better performance gains...any links or info would be greatly appreciated."
I read some DDR boards only offered a 4-5% improvement over pc133(!) on some tests!
These were the early boards. But still!
How is Apple going to increase it's performance by 100%?
Quads? Software? New co-processor chipset? G5? New Nvidia/Apple graphics card? 4 megs of level 3 cache? 1.6 dual g4s? Dual core G3 with new simd unit?
I'm open to ideas. I'm pretty fluid to an open and well reasoned argument right about now...
<strong>Again, I'm curious as to what Apple will have left to show come Macworld New York.
If ibooks are revised next week...then? Then what?
Just 'Power'mac revisions? A shipping date for Jaguar? A bump to the imac?
After a whole half a year...I find it incredulous to believe we'll only see 1.2 gig G4 macs.
A bump of 200mhz? :eek:
Maybe, like with Quartz Extreme on the OS front,
...like Blast on the science front...
...like altivec on the dvd front...
Digital Video and 3D are becoming increasingly important to apple.
If they aren't ready for true 'G5' processors with rapid io which I think most agree is the way optimistic for Macworld New York...then it's just a speed bump to Apollo in the 1 -1.2 gig or 1 - 1.4 gig range. And yes, with some form of DDR implementation.
But Mosr (now, now...stay with me a minute here...) says: new cases and 100% faster.
Where's that extra speed coming from?
A few hints say: specs will look ordinary and we'll scream blue murder... So if Apple haven't been able to get the mhz beyond 1.2 gig. Then...what?
Special hardware accleleration? A form of 'Blast' but for 3D? Didn't Raycer have some form of special 3d algorithm (spelling excuse, mental blank...) technology for reducing 3d work undertaken by 3D chip?
100% is a big leap in processing power. That's the equivalent of several 'Power'mac cpu speed bumps and a mobo revision. Where's it coming from? I don't think a cpu bump and mobo revision is going to cover that?
Apple don't control the cpu making directly. But they, to be fair, try to compensate to some degree by offering some 'gimmick', whether it's dual processor across the line or 'blast' or Quartz Extreme.
IF we do get 1.2 gig processors and a slight Mobo revision...
...then what do YOU guys think they'll have up Steve's sleeve? More reality distortion? This time, I think not...
yours thoughtfully,
Lemon Bon Bon </strong><hr></blockquote>
Ehh....I'm guessing 50% speed increase, going to 1.4GHz DP, DDR-RAM, and Jaguar. I'm also betting that they stay with the 133MHz bus. We will also get a new SuperDrive, though it probably wont be called SuperDrive 2. Might be called something different, but Not SuperDrive 2.
Let's all take a moment to go to Apple.com and pull up the server architecture and behold that big chip in the middle. And Steve even made a point of it. If you look you will see that the Apple ASIC is connected to memory and the CPU's are connected to the ASIC. In this configuration it would seem that the ASIC gets data from wherever and presents it to whatever needs to get that data. Now replace the 133MHz interface between the CPUs and the ASIC with a rapidIO interface and then the bandwidth is 4gigabyte not one gigabyte. Now if Moto comes out with a chip that supports Altivec and has some improved FPU tweaks and or another FPU unit and OCEAN, most of which is in production. Then each chip could share the 2gigabyte bandwidth that the ASIC shares with main memory. Now if Apple were to make a 128 bit bus to memory that would be huge bandwidth. My personal wishes are for ibm to make the next chip and utilize hypertransport rather than RapidIO and for Apple to license Altivec for inclusion in that chip.
<strong>Let's all take a moment to go to Apple.com and pull up the server architecture and behold that big chip in the middle. And Steve even made a point of it. If you look you will see that the Apple ASIC is connected to memory and the CPU's are connected to the ASIC. In this configuration it would seem that the ASIC gets data from wherever and presents it to whatever needs to get that data. Now replace the 133MHz interface between the CPUs and the ASIC with a rapidIO interface and then the bandwidth is 4gigabyte not one gigabyte. Now if Moto comes out with a chip that supports Altivec and has some improved FPU tweaks and or another FPU unit and OCEAN, most of which is in production. Then each chip could share the 2gigabyte bandwidth that the ASIC shares with main memory. Now if Apple were to make a 128 bit bus to memory that would be huge bandwidth. My personal wishes are for ibm to make the next chip and utilize hypertransport rather than RapidIO and for Apple to license Altivec for inclusion in that chip.</strong><hr></blockquote>
Never thought about that...that would certianly open up the chokehold on the DDR-RAM and to spare...
Comments
<strong>Do you even know what you're talking about? There's no such thing as a 'ddr frontside bus' or whatever. 'ddr frontside buses' run at 133 mhz [so far].</strong><hr></blockquote>
There is no such thing as a DDR front side MPX bus yet. That doesn't mean Motorola doesn't have one coming in the next iteration of the G4. It would allow them to double the bandwidth without increasing the bus clock rate (which is a more difficult task since all the signals then need to run at an increased rate).
I wanted to believe the G5 was coming any day now for the better part of a year, Finally, however, I am beginning to face reality. I, like so many others, want a revolutionary turn of events for Apple. We want Apple to blow the competition away. The truth, however, is the revolution won?t happen overnight. It will be long and slow, and, while requiring a lot of work from Apple, will probably seem quite boring. The G5 will come someday, but probably not at MWNY. When it finally arrives, the surrounding competition will make it about as exciting to us as the G4 is now. <hr></blockquote>
I've lived a little over 24 hours with my new reality policy. Let me just say, reality is a harsh mistress. I'm returning to my previous methods of dealing with the situation.
<strong>
I've lived a little over 24 hours with my new reality policy. Let me just say, reality is a harsh mistress. I'm returning to my previous methods of dealing with the situation.
Well, one thing to realize: the longer you hold out hope for the G5, the more likely it is that you will be correct.
because most apple users are fanatics ,and i am one to.
but why are we waiting for those chips.
is it realy gonna effect the way we computer?
apple is faster anyway but pc users just dont admit it, well we know better.
i even bet that almost none of us have the fastest g4 so it is not gonna change the way you computer ,when the time is there apple will introduce an 2 ghz machine you wil be computering with an 933 so lets wait for a real anwser to this question.
grtz
[ 05-19-2002: Message edited by: jonasvdl ]
Thanks.
As for a double-pumped MPX bus, I followed a link over to Ars Technica and read a few lengthy musings by BadAndy. This is what I was able to snatch from the words that went over my head:
The MaxBus is incredibly elaborate (too elaborate in his opinion). In addition to useful things like reserving (a processor tells the bus that it will receive the next X amount of information, greatly simplifying arbitration) and streaming (near 100% bus efficiency if the bus knows what's coming), it's designed to handle transactions with devices at all different levels of latency, throughput and even reliability. In other words, it's hopelessly overengineered for the work Apple requires it to do. Armed with this knowledge, and acknowledging that enough might have flown over my head that I got a few things wrong, suddenly Mot's "stalling" makes sense: It's really easy to double-pump a simple bus, but MPX is designed to have so many things going on at once, with so many caveats and conditions and contingencies (example: It can handle three failed requests per cycle with no loss of bandwidth), that getting it all to run twice as fast might be a real task. BadAndy speculates that a double-pumped MPX bus will abandon a number of the features of the original bus (hopefully the ones that Apple doesn't rely on!). But if the bus changes substantively, rather than just doing the same thing faster, then the memory controller has to be changed substantively as well, and all of a sudden there's a lot of work to do for both companies.
BTW, BadAndy and another poster determined that DDR RAM actually does help performance across MaxBus: It reduces latency. That's not an earthshaking improvement, but it certainly helps.
[ 05-19-2002: Message edited by: Amorph ]</p>
maybe they're just waiting for moto to do their part now.
<img src="graemlins/smokin.gif" border="0" alt="[Chilling]" />
If ibooks are revised next week...then? Then what?
Just 'Power'mac revisions? A shipping date for Jaguar? A bump to the imac?
After a whole half a year...I find it incredulous to believe we'll only see 1.2 gig G4 macs.
A bump of 200mhz? :eek:
Maybe, like with Quartz Extreme on the OS front,
...like Blast on the science front...
...like altivec on the dvd front...
Digital Video and 3D are becoming increasingly important to apple.
If they aren't ready for true 'G5' processors with rapid io which I think most agree is the way optimistic for Macworld New York...then it's just a speed bump to Apollo in the 1 -1.2 gig or 1 - 1.4 gig range. And yes, with some form of DDR implementation.
But Mosr (now, now...stay with me a minute here...) says: new cases and 100% faster.
Where's that extra speed coming from?
A few hints say: specs will look ordinary and we'll scream blue murder... So if Apple haven't been able to get the mhz beyond 1.2 gig. Then...what?
Special hardware accleleration? A form of 'Blast' but for 3D? Didn't Raycer have some form of special 3d algorithm (spelling excuse, mental blank...) technology for reducing 3d work undertaken by 3D chip?
100% is a big leap in processing power. That's the equivalent of several 'Power'mac cpu speed bumps and a mobo revision. Where's it coming from? I don't think a cpu bump and mobo revision is going to cover that?
Apple don't control the cpu making directly. But they, to be fair, try to compensate to some degree by offering some 'gimmick', whether it's dual processor across the line or 'blast' or Quartz Extreme.
IF we do get 1.2 gig processors and a slight Mobo revision...
...then what do YOU guys think they'll have up Steve's sleeve? More reality distortion? This time, I think not...
yours thoughtfully,
Lemon Bon Bon
Going quad would do exactly that! Increase performance 100%. At least theoretically, and this is not an official statement so why bother with such details
If moto is coming through with a 266 MHz DDR system bus, why shouldn't apple make the absolute most of it?
It would cost, of course, but apple desperately needs as much PM performance as the can get.
<strong>That 100% performance increase rumour is the very reason I've been suspecting Quads are coming. IF it is true that is.
Going quad would do exactly that! Increase performance 100%. At least theoretically, and this is not an official statement so why bother with such details
If moto is coming through with a 266 MHz DDR system bus, why shouldn't apple make the absolute most of it?
It would cost, of course, but apple desperately needs as much PM performance as the can get.</strong><hr></blockquote>
Because putting twice as many of the most expensive, hottest, and highest pin count parts into your system will greatly impact the pricing... and you won't get anything close to a 100% performance improvement. You'd be doing well to hit 50-75%. Now, if these things were multicore, then that's another story.
<strong>That 100% performance increase rumour is the very reason I've been suspecting Quads are coming. IF it is true that is.
Going quad would do exactly that! Increase performance 100%. At least theoretically, and this is not an official statement so why bother with such details
If moto is coming through with a 266 MHz DDR system bus, why shouldn't apple make the absolute most of it?
It would cost, of course, but apple desperately needs as much PM performance as the can get.</strong><hr></blockquote>
DDR only adds 10% - 15% speed increase (mostly latency) in PC's. Apple uses a different bus achitecture. The question is "Is the Apple memory bus already giving speed increases similar to those obtained from DDR in peecees?".
Another question, What is the speed advantage of DDR cache versus DDR FSB and how does that effect overall system speed? Maybe DDR FSB is not relevant to Apple. What really needs to be done is increased bandwidth of the G4 combined with the new i/o system in the ServeX.
<strong>Just where is that rumor about 100 % speed increase from??
Only place I heard of the 100% increase was at xlr8.com in a comment by Mike to another reader in a Forum.
<strong>
DDR only adds 10% - 15% speed increase (mostly latency) in PC's. Apple uses a different bus achitecture. The question is "Is the Apple memory bus already giving speed increases similar to those obtained from DDR in peecees?".
...</strong><hr></blockquote>
Is this really true? I know the first gen DDR boards had about this much speed increase, but is that true now? The increased memory bandwidth is substantial, most things I have read indicate much better performance gains...any links or info would be greatly appreciated.
<strong>
Is this really true? I know the first gen DDR boards had about this much speed increase, but is that true now? The increased memory bandwidth is substantial, most things I have read indicate much better performance gains...any links or info would be greatly appreciated.</strong><hr></blockquote>
Read the whole article and references- interesting info.
(edit: It's a little different for the new P4 chips)
<a href="http://www6.tomshardware.com/mainboard/00q4/001030/athlon-15.html"; target="_blank">http://www6.tomshardware.com/mainboard/00q4/001030/athlon-15.html</a>;
[ 05-19-2002: Message edited by: Bigc ]</p>
I read some DDR boards only offered a 4-5% improvement over pc133(!) on some tests!
These were the early boards. But still!
How is Apple going to increase it's performance by 100%?
Quads? Software? New co-processor chipset? G5? New Nvidia/Apple graphics card? 4 megs of level 3 cache? 1.6 dual g4s? Dual core G3 with new simd unit?
I'm open to ideas. I'm pretty fluid to an open and well reasoned argument right about now...
Lemon Bon Bon
[ 05-19-2002: Message edited by: Lemon Bon Bon ]
[ 05-19-2002: Message edited by: Lemon Bon Bon ]</p>
<strong>Again, I'm curious as to what Apple will have left to show come Macworld New York.
If ibooks are revised next week...then? Then what?
Just 'Power'mac revisions? A shipping date for Jaguar? A bump to the imac?
After a whole half a year...I find it incredulous to believe we'll only see 1.2 gig G4 macs.
A bump of 200mhz? :eek:
Maybe, like with Quartz Extreme on the OS front,
...like Blast on the science front...
...like altivec on the dvd front...
Digital Video and 3D are becoming increasingly important to apple.
If they aren't ready for true 'G5' processors with rapid io which I think most agree is the way optimistic for Macworld New York...then it's just a speed bump to Apollo in the 1 -1.2 gig or 1 - 1.4 gig range. And yes, with some form of DDR implementation.
But Mosr (now, now...stay with me a minute here...) says: new cases and 100% faster.
Where's that extra speed coming from?
A few hints say: specs will look ordinary and we'll scream blue murder... So if Apple haven't been able to get the mhz beyond 1.2 gig. Then...what?
Special hardware accleleration? A form of 'Blast' but for 3D? Didn't Raycer have some form of special 3d algorithm (spelling excuse, mental blank...) technology for reducing 3d work undertaken by 3D chip?
100% is a big leap in processing power. That's the equivalent of several 'Power'mac cpu speed bumps and a mobo revision. Where's it coming from? I don't think a cpu bump and mobo revision is going to cover that?
Apple don't control the cpu making directly. But they, to be fair, try to compensate to some degree by offering some 'gimmick', whether it's dual processor across the line or 'blast' or Quartz Extreme.
IF we do get 1.2 gig processors and a slight Mobo revision...
...then what do YOU guys think they'll have up Steve's sleeve? More reality distortion? This time, I think not...
yours thoughtfully,
Lemon Bon Bon
Ehh....I'm guessing 50% speed increase, going to 1.4GHz DP, DDR-RAM, and Jaguar. I'm also betting that they stay with the 133MHz bus. We will also get a new SuperDrive, though it probably wont be called SuperDrive 2. Might be called something different, but Not SuperDrive 2.
<strong>Let's all take a moment to go to Apple.com and pull up the server architecture and behold that big chip in the middle. And Steve even made a point of it. If you look you will see that the Apple ASIC is connected to memory and the CPU's are connected to the ASIC. In this configuration it would seem that the ASIC gets data from wherever and presents it to whatever needs to get that data. Now replace the 133MHz interface between the CPUs and the ASIC with a rapidIO interface and then the bandwidth is 4gigabyte not one gigabyte. Now if Moto comes out with a chip that supports Altivec and has some improved FPU tweaks and or another FPU unit and OCEAN, most of which is in production. Then each chip could share the 2gigabyte bandwidth that the ASIC shares with main memory. Now if Apple were to make a 128 bit bus to memory that would be huge bandwidth. My personal wishes are for ibm to make the next chip and utilize hypertransport rather than RapidIO and for Apple to license Altivec for inclusion in that chip.</strong><hr></blockquote>
Never thought about that...that would certianly open up the chokehold on the DDR-RAM and to spare...
<strong>How is Apple going to increase it's performance by 100%? </strong><hr></blockquote>
OK, 85% more memory throughput will give Steve 85% more speed in some PhotoShop demonstrations he likes so much. Add 1,2 GHz G4s and you've got it
FYI: SDRAM 133MHz SDR gives you 975 MB/s throughput reading one memory line, DDR 1800 MB/s.
Reading 1 Byte at once this goes down to 20 MB/s for both. This is maximum and mimimum for a 133 MHz bus (2-2-2 memory timing).
<strong>
Only place I heard of the 100% increase was at xlr8.com in a comment by Mike to another reader in a Forum.</strong><hr></blockquote>
MOSR posted it then pulled it a day or two later