I finally got the Book E Reference Manual now as well as some 64 bit PowerPC specific documentation, but unfortunaly I didn't have much time to read yet. The Book E manual alone has almost 500 pages, so it will take me some time to take a closer look.
The main difference between the G4 and the G5 is that the G5 is Book E compliant. This means that all features that are listed in the E reference must be present in the G5, and the cpu must handle all instructions exactly as described in the reference.
As far as I can see now Book E tells us nothing about RapidIO or DDR, it only covers the instruction set and basic behaviour.
Just like the original PowerPC design, Book E describes a 64 bit architecture with a 32 bit subset, thus it will be possible to build 32 and 64 bit products. Some people believe that a Book E processor will always be 64 bit, but if you take a closer look at the reference you will notice that this ain't true.
The 64 and 32 bit implementation are almost the same, except for the register with and some instructions. There are instructions that work only in 64 bit mode, while there are similar versions of the instructions that are only working in 32 bit mode (there are very few of those). Other instructions are totally new and can only be used with 64 bit PowerPC processors, I haven't counted them yet but there seems to be a certain number of those.
A Book E processor can natively execute existing PowerPC code, but only of this code meets prior specifications (this should be true for software done with the most common compilers). A 64 bit processor will have to switch to 32 bit mode to execute older binaries.
A 64 bit Book E processor can execute both 64 bit and 32 bit code, but a 32 bit processor cannot execute 64 bit code (ok, I suppose you know this...). A 64 bit Book E processor can switch to the 32 mode (and back to the 64 bit mode) simply by setting a bit in the MSR (machine state register) in supervisor mode. This means that you will be able to run 32 and 64 bit applications at the same time (multitasking), as the kernel handles the MSR. The 32 bit mode for 64 bit PowerPC processors is not an emulation, the processor only limits the registers. Therefore 32 bit code will not be slower than with current 32 bit processors.
The instruction set compatibility with current PowerPC chips is true for all user mode instructions, but - as far as I can say for now - not necessary in supervisor mode. Probably the current OSX kernel would not run on a Book E cpu (aka G5), but a simple recompile with an updating compiler should make it work.
Ok, that's all for now, I'll write again as soon as I know more...
Despite the authority with which Eric DVH speaks, there is no official information about this chip -- just a lot of fast and loose speculaton.
[quote]
This wouldn't effect the RapidIO. as the PCI-X controller is also on-chip.
<hr></blockquote>
Thus far I've seen no rumours about the PCI-X controller on the chip, and this seems like an unlikely thing to do. Designing new processor chips (even modular ones) is expensive so its far more effective to have one system interface (RapidIO) and hang all other busses on that. Multiple PCI-X controllers could then be attached if you could work out the addressing issues.
[quote]
Because the RAM industry is greedy and evil. even I am starting to wonder if those rumors of subterranean DIMM silos in the midwest are true .
<hr></blockquote>
No, its because there is latency in the memory production process and demand is cyclical. Demand goes up, production eventually rises to meet demand, but then demand drops off and there is way too much supply. Prices are low, and production is reduced. Demand then climbs again, and supply is inadequate. Prices are then high. Read this: <a href="http://www.macedition.com/op/op_ram_20020410.php"; target="_blank">http://www.macedition.com/op/op_ram_20020410.php</A>;
[quote]
AGP 8x ain't here yet.
<hr></blockquote>
As I said above, CPUs take a while to design and deliver... we'd rather not wait for a new CPU to get faster busses, right?
[quote][b]
Originally posted by Programmer:
-Motherboard based graphics chips could easily consume 4-8 GB/sec.
[b]
I wish!
[quote]
The day isn't far away.
[quote]
You've got to be kidding! stuffing everything onto a daughterboard would make the machines nearly impossible to upgrade. as well as making high-end MP systems(Four CPUs and up) ungodly expensive and inflexible.
CPUs need their own dedicated SRAM cache in order to have somewhere to put large numbers of variables. and all CPUs as a whole(Also other components like graphics and sound chipsets. as I favor unified memory architectures ) require a large pool of equally accessible memory as well.
This is easily verifiable though. as anyone with a near-final prototype G5 could just pop open the case and see whether or not everything's crammed onto a daughterboard.
<hr></blockquote>
Did you even bother to read Dorsal M's posts? You know, the guy who started this thread that did exactly what you just suggested?
And local processor memory is a very valid concept, used in many kinds of systems -- for Apple to take a radical approach like that could be their first real attempt to differentiate the Mac in a long time.
[quote]
RapidIO scales up to 8MBps. by "Discussed". do you mean the one that will actually be on the very first G5 when it ships?
<hr></blockquote>
Yes -- as I said above, if you build things into the processor you run the risk of delaying improvements in the system until the next processor revision. And we all know Motorola's track record on that score.
[quote]
DDR 2700 is already onboard the G5. they've chosen. it's done. no turning back.
<hr></blockquote>
Uh huh... and you've proven this how? Dorsal's messages at the top of this thread talk about DDR333, but historically his machines have been very early prototypes -- either never destined for production, or a long way from it. Nonetheless, DDR2700 wouldn't surprise me at all in the next set of machines, its what I'm hoping for at a minimum.
[quote]
So what? many CPUs use a 64-bit bus and 32-bit addressing. but 1 byte still equals 8 bits whenever you're referring to hard disks, RAM, throughput etc.
Let's just keep things simple and stick with 8-bit bytes for measurement. to convert from Mbps to MBps. divide by 8. not 16.
<hr></blockquote>
Yes... but if somebody gives you the MHz, not the MBps then you need to know the bus width.
[quote]
You've got to be kidding! stuffing everything onto a daughterboard would make the machines nearly impossible to upgrade. as well as making high-end MP systems(Four CPUs and up) ungodly expensive and inflexible.
<hr></blockquote>
Or for the first time you can upgrade the memory in these machines, making them more upgradable. Plus you can upgrade their memory bandwidth by adding processors. Again, did you read Dorsal M's post? I'm not pulling this stuff out of thin air.
[quote]
The cache isn't SRAM.
<hr></blockquote>
Yes, it is. If it was just DDR SDRAM then the advantage of using it would be practically nil.
[quote]
Speaking of driver issues. do any of you think will nVidia/ATI ever enable FSAA, motion blur etc. on older Mac chipsets(GeForce2 MX for example?)? those jagged edges are really irritating.
<hr></blockquote>
Earlier chipsets don't really have the pixel rate to support it.
[quote]
You mean like the external FPUs on the old 68ks? that would've been a pretty cool way for Apple to introduce AltiVec without forcing the issue. and it might even be a nifty option on G3 based iBooks(Most of all. I wish they'd bring back the Duo ). but I can't imagine it adding anything other than latency on Apple's "Big" CPU.
Anyone know if Apple will be upgrading Firewire to IEEE1394b? Or will that be available when G6 is released.
AirPort could use a little tuning up by upgrading its wireless technology to 802.11a, and maybe even support WEP?
Proxim is releasing an 802.11a wireless hub for Macs this year, and could prove to be some noteworthy competition for Apple's AirPort. Anyone know the status on Apple's wireless future?
The framerate hits are just WAY too much unless you have a fantastic system (top of the line PC, GF4 and all ). But...it's not really necessary at resolutions above 800x600. At higher resolutions, the 'jaggies' start to fade. I run 1024x768 on my G4 400 Sawtooth (Radeon, 1.4GB RAM), the 'jaggies' are hardly noticable and I average over 60fps on the Quake 3 "demo four."
The smaller everything is (due to resolution), the less noticable they are. At least, I think so.
[quote]DDR 2700 is already onboard the G5. they've chosen. it's done. no turning back.
<hr></blockquote>
The book E compliant CPU on Moto's website (8[45]xx?) lists DDR 333 RAM, which I suppose is PC2700. Perhaps it's they == Mac rumourists have chosen and decided that this is definitely a G5
, and AIM had better not turn back
Pop your proto-G5 case open and watch as you or your organisation never gets one again...
<strong>Not so. wintel owners have been able to buy $100-$300 HDTV tuners like this and this for over three years now.</strong><hr></blockquote>
While I can't comment on the full rant/message... Eric D.V.H. has proven to me that he knows LESS THAN nothing about HDTV tuner cards.
That statement above is total BS pure and simple. I know that for a FACT! Now you just have to ask yourself... 'if he pulled that outta his @ss then what else is he BSing about?
Sorry but HT is a huge and EXPENSIVE hobby of mine and tring to tell me PC's running windows (or any other OS for that matter) have had access to $100 HDTV tuners for 3 PLUS years is a joke... (and makes you look very very foolish).
[quote]Originally posted by Exercise in Frivolity:
<strong>Mmmm, rampant speculation...
I guess that's what these forums are for though. However, I somehow doubt he knows much more (if anything) than the rest of us.</strong><hr></blockquote>
Comments
<strong>
either you know something most people don't or you sound just very confident. please elaborate...</strong><hr></blockquote>
Mmmm, rampant speculation...
I guess that's what these forums are for though. However, I somehow doubt he knows much more (if anything) than the rest of us.
The main difference between the G4 and the G5 is that the G5 is Book E compliant. This means that all features that are listed in the E reference must be present in the G5, and the cpu must handle all instructions exactly as described in the reference.
As far as I can see now Book E tells us nothing about RapidIO or DDR, it only covers the instruction set and basic behaviour.
Just like the original PowerPC design, Book E describes a 64 bit architecture with a 32 bit subset, thus it will be possible to build 32 and 64 bit products. Some people believe that a Book E processor will always be 64 bit, but if you take a closer look at the reference you will notice that this ain't true.
The 64 and 32 bit implementation are almost the same, except for the register with and some instructions. There are instructions that work only in 64 bit mode, while there are similar versions of the instructions that are only working in 32 bit mode (there are very few of those). Other instructions are totally new and can only be used with 64 bit PowerPC processors, I haven't counted them yet but there seems to be a certain number of those.
A Book E processor can natively execute existing PowerPC code, but only of this code meets prior specifications (this should be true for software done with the most common compilers). A 64 bit processor will have to switch to 32 bit mode to execute older binaries.
A 64 bit Book E processor can execute both 64 bit and 32 bit code, but a 32 bit processor cannot execute 64 bit code (ok, I suppose you know this...). A 64 bit Book E processor can switch to the 32 mode (and back to the 64 bit mode) simply by setting a bit in the MSR (machine state register) in supervisor mode. This means that you will be able to run 32 and 64 bit applications at the same time (multitasking), as the kernel handles the MSR. The 32 bit mode for 64 bit PowerPC processors is not an emulation, the processor only limits the registers. Therefore 32 bit code will not be slower than with current 32 bit processors.
The instruction set compatibility with current PowerPC chips is true for all user mode instructions, but - as far as I can say for now - not necessary in supervisor mode. Probably the current OSX kernel would not run on a Book E cpu (aka G5), but a simple recompile with an updating compiler should make it work.
Ok, that's all for now, I'll write again as soon as I know more...
BTW, is the Register fairly reliable?
No.
<strong>BTW, is the Register fairly reliable?</strong><hr></blockquote>
Not bad.
It's as good as it's sources, and they are the same ones we have.
<strong>
I won't call it a G5 unless it says "85xx" somewhere on it. and I doubt most others will either.
</strong><hr></blockquote>
Who cares what the part number is as long as it's fast?
[quote]
This wouldn't effect the RapidIO. as the PCI-X controller is also on-chip.
<hr></blockquote>
Thus far I've seen no rumours about the PCI-X controller on the chip, and this seems like an unlikely thing to do. Designing new processor chips (even modular ones) is expensive so its far more effective to have one system interface (RapidIO) and hang all other busses on that. Multiple PCI-X controllers could then be attached if you could work out the addressing issues.
[quote]
Because the RAM industry is greedy and evil. even I am starting to wonder if those rumors of subterranean DIMM silos in the midwest are true .
<hr></blockquote>
No, its because there is latency in the memory production process and demand is cyclical. Demand goes up, production eventually rises to meet demand, but then demand drops off and there is way too much supply. Prices are low, and production is reduced. Demand then climbs again, and supply is inadequate. Prices are then high. Read this: <a href="http://www.macedition.com/op/op_ram_20020410.php"; target="_blank">http://www.macedition.com/op/op_ram_20020410.php</A>;
[quote]
AGP 8x ain't here yet.
<hr></blockquote>
As I said above, CPUs take a while to design and deliver... we'd rather not wait for a new CPU to get faster busses, right?
[quote][b]
Originally posted by Programmer:
-Motherboard based graphics chips could easily consume 4-8 GB/sec.
[b]
I wish!
[quote]
The day isn't far away.
[quote]
You've got to be kidding! stuffing everything onto a daughterboard would make the machines nearly impossible to upgrade. as well as making high-end MP systems(Four CPUs and up) ungodly expensive and inflexible.
CPUs need their own dedicated SRAM cache in order to have somewhere to put large numbers of variables. and all CPUs as a whole(Also other components like graphics and sound chipsets. as I favor unified memory architectures ) require a large pool of equally accessible memory as well.
This is easily verifiable though. as anyone with a near-final prototype G5 could just pop open the case and see whether or not everything's crammed onto a daughterboard.
<hr></blockquote>
Did you even bother to read Dorsal M's posts? You know, the guy who started this thread that did exactly what you just suggested?
And local processor memory is a very valid concept, used in many kinds of systems -- for Apple to take a radical approach like that could be their first real attempt to differentiate the Mac in a long time.
[quote]
RapidIO scales up to 8MBps. by "Discussed". do you mean the one that will actually be on the very first G5 when it ships?
<hr></blockquote>
Yes -- as I said above, if you build things into the processor you run the risk of delaying improvements in the system until the next processor revision. And we all know Motorola's track record on that score.
[quote]
DDR 2700 is already onboard the G5. they've chosen. it's done. no turning back.
<hr></blockquote>
Uh huh... and you've proven this how? Dorsal's messages at the top of this thread talk about DDR333, but historically his machines have been very early prototypes -- either never destined for production, or a long way from it. Nonetheless, DDR2700 wouldn't surprise me at all in the next set of machines, its what I'm hoping for at a minimum.
[quote]
So what? many CPUs use a 64-bit bus and 32-bit addressing. but 1 byte still equals 8 bits whenever you're referring to hard disks, RAM, throughput etc.
Let's just keep things simple and stick with 8-bit bytes for measurement. to convert from Mbps to MBps. divide by 8. not 16.
<hr></blockquote>
Yes... but if somebody gives you the MHz, not the MBps then you need to know the bus width.
[quote]
You've got to be kidding! stuffing everything onto a daughterboard would make the machines nearly impossible to upgrade. as well as making high-end MP systems(Four CPUs and up) ungodly expensive and inflexible.
<hr></blockquote>
Or for the first time you can upgrade the memory in these machines, making them more upgradable. Plus you can upgrade their memory bandwidth by adding processors. Again, did you read Dorsal M's post? I'm not pulling this stuff out of thin air.
[quote]
The cache isn't SRAM.
<hr></blockquote>
Yes, it is. If it was just DDR SDRAM then the advantage of using it would be practically nil.
[quote]
Speaking of driver issues. do any of you think will nVidia/ATI ever enable FSAA, motion blur etc. on older Mac chipsets(GeForce2 MX for example?)? those jagged edges are really irritating.
<hr></blockquote>
Earlier chipsets don't really have the pixel rate to support it.
[quote]
You mean like the external FPUs on the old 68ks? that would've been a pretty cool way for Apple to introduce AltiVec without forcing the issue. and it might even be a nifty option on G3 based iBooks(Most of all. I wish they'd bring back the Duo ). but I can't imagine it adding anything other than latency on Apple's "Big" CPU.
<hr></blockquote>
Its just not feasible these days.
Anyone know if Apple will be upgrading Firewire to IEEE1394b? Or will that be available when G6 is released.
AirPort could use a little tuning up by upgrading its wireless technology to 802.11a, and maybe even support WEP?
Proxim is releasing an 802.11a wireless hub for Macs this year, and could prove to be some noteworthy competition for Apple's AirPort. Anyone know the status on Apple's wireless future?
<img src="confused.gif" border="0">
The framerate hits are just WAY too much unless you have a fantastic system (top of the line PC, GF4 and all
The smaller everything is (due to resolution), the less noticable they are. At least, I think so.
kormac and Dorsal have a contest going on, who gives in first and posts again....
[ 04-23-2002: Message edited by: Bodhi ]</p>
<hr></blockquote>
The book E compliant CPU on Moto's website (8[45]xx?) lists DDR 333 RAM, which I suppose is PC2700. Perhaps it's they == Mac rumourists have chosen and decided that this is definitely a G5
, and AIM had better not turn back
Pop your proto-G5 case open and watch as you or your organisation never gets one again...
[quote]leave the FSB alone.<hr></blockquote>
:eek:
<strong>Not so. wintel owners have been able to buy $100-$300 HDTV tuners like this and this for over three years now.</strong><hr></blockquote>
While I can't comment on the full rant/message... Eric D.V.H. has proven to me that he knows LESS THAN nothing about HDTV tuner cards.
That statement above is total BS pure and simple. I know that for a FACT! Now you just have to ask yourself... 'if he pulled that outta his @ss then what else is he BSing about?
Sorry but HT is a huge and EXPENSIVE hobby of mine and tring to tell me PC's running windows (or any other OS for that matter) have had access to $100 HDTV tuners for 3 PLUS years is a joke... (and makes you look very very foolish).
D
Not saying that anyone's crossed the line; it's just that I'd rather prevent that if possible.
Carry on.
<strong>either you know something most people don't or you sound just very confident. please elaborate...</strong><hr></blockquote>
Surely. read Motorola's <a href="http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=01M98655"; target="_blank">webpage on the PPC 8540</a>. I prefer to use the 8540 as a bottom line against which to hold the CPU that will most likely be in Apple's PowerMac G5.
Eric,
[ 04-24-2002: Message edited by: Eric D.V.H ]</p>
<strong>Mmmm, rampant speculation...
I guess that's what these forums are for though. However, I somehow doubt he knows much more (if anything) than the rest of us.</strong><hr></blockquote>
Me too. I think the vast bulk of you have already <a href="http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=01M98655"; target="_blank">been here</a>.
Eric,
<strong>
Me too. I think the vast bulk of you have already <a href="http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=01M98655"; target="_blank">been here</a>.
Eric,</strong><hr></blockquote>
Sure have. Long ago. Has nothing to do with the G5.
<strong>Who cares what the part number is as long as it's fast?</strong><hr></blockquote>
Ahh. but how fast? I think I'd feel short shrifted if all the PowerMac G5 had in it was a slightly enhanced G4.
Eric,
[ 04-24-2002: Message edited by: Eric D.V.H ]</p>