<strong>... In fact, I believe the impedence should be low enough to allow for 4 DIMM slots.</strong><hr></blockquote>
Just curious what you mean by that... Characteristic impedance of the traces? Output impedance of the driver?
Transmission line theory was a long time ago so it wouldn't surprise me if I am missing something, but how does that affect the load driving capability of the design? Even with transceivers, that's a pretty big load for anything to drive and relatively high speeds!
rickag, there already is a crimp on upgraders. I have yet to see a non-Apple 500MHz+ upgrade for any Apple machine. Although this may be because of minimum quantity bought is too high now.
<strong>anyway what he said sound real. He just give further detail about the size of the mobo and daughter card which need an certain expertise.
but he did not say :
what is the ata bus : ata 66, 100 , 133 or serial ata ?
amount of L2 cache of the 7500 : 256 KByte or 512 KByte ?
Firewire first generation or firewire second generation
USB or USB 2.
What video card did he see in it ...
If you where able Dorsal M to see that rapid I/O and PCI X was implemanted you will be able to answers at these questions (perhaps not the size of the L2 cache)</strong><hr></blockquote>
Remember this was a prototype most probably designed just to test specific bits so its unlikely it has full spec parts like HDDs, graphics cards etc. If they added it all in there any bugs would be much harder to find.
There might be other beta boxes with various ATA controllers, firewire chipsets etc all designed to iron out problems in those features. Then eventually all the parts will be brought together in one box.
unless he's making an assumption about who made the chips, i believe he's wrong. motorola isn't making the g5 for apple. although the timing seems about right, just not the source of the chip.</strong><hr></blockquote>
Got that feeling myself, the contract with Moto is up this summer, Apple may opt for IBM. Which would be better since IBM makes lots of different CPUs and is a hired gun to manufacture anything that is thrown at them. I think that it is obvious that Moto is concentrating on the embedded market, at least the embedded market that has little in common with G5 chips.
Are these for WWDC in May or MWNY in July? I'm guessing July. I hope something like this is announced to ship in July (or August or September or ...). I've got money for one. My Smurf G3/400 is sloooow ripping MP3 and surfing the web under X.
<strong>Are these for WWDC in May or MWNY in July? I'm guessing July. I hope something like this is announced to ship in July (or August or September or ...). I've got money for one. My Smurf G3/400 is sloooow ripping MP3 and surfing the web under X.</strong><hr></blockquote>
Those are my two biggest probs in X right now...iTunes and every other MP3 app is dog slow. IE is slightly slower on load speed...but the main prob is scrolling. My other main problem is AIM..but I only use that for file trans. Go Adium!
At least it's a specific report, and not something about having 6 different G5s, all with different motherboards, different types of RAM, different buses, etc. I find this Dorsal report more believable than some others, but still it's not very believable. Doesn't Apple SEAL the prototype hardware that gets seeded? And if not, then aren't there only a few developers that would need hardware access, and thus wouldn't it be easy for Apple to track down Dorsal's identity?
<strong>At least it's a specific report, and not something about having 6 different G5s, all with different motherboards, different types of RAM, different buses, etc. I find this Dorsal report more believable than some others, but still it's not very believable. Doesn't Apple SEAL the prototype hardware that gets seeded? And if not, then aren't there only a few developers that would need hardware access, and thus wouldn't it be easy for Apple to track down Dorsal's identity?</strong><hr></blockquote>
I was wondering that too. But we're assuming Dorsal M is one developer. Maybe its a group (network?) of people who feed one source - a deep throat if you like.
We'll never know, but italways seems his posts are well researched and therefore more beleivable.
If Dorsal is the real thing (ex. a developer) I think his actions are approved by someone at Apple... I think he is just a way of leaking a few details to the public to keep the interest alive.
Anyways I do believe what he is saying is true as far as internal development goes, but a prototype is one thing, while the shipping product is another.
[quote]I forget... is "Dorsal M" the original Dorsal, or one of the poseurs?<hr></blockquote>
You'd think Apple would have clamped down on this leak if he was actually describing real prototypes...
Anyway, at least kormac tried a bit harder. Either kormac was from Korea or he spent some time looking for a korean proxy server. And kormac's speculation was a lot more entertaining.
And if you scrutinize some parts of e-www.motorola.com, it's not hard to figure out why one would believe in the existence of an MPC7500.
<strong>At least it's a specific report, and not something about having 6 different G5s, all with different motherboards, different types of RAM, different buses, etc. I find this Dorsal report more believable than some others, but still it's not very believable. Doesn't Apple SEAL the prototype hardware that gets seeded? And if not, then aren't there only a few developers that would need hardware access, and thus wouldn't it be easy for Apple to track down Dorsal's identity?</strong><hr></blockquote>
Earlier in product development there are generally more wildly varying configurations. As the product develops it narrows down to a more specific design. As it gets closer to the final hardware it becomes more advisable to allow 3rd parties closer access, and thus more knowledge. The above message (and the ones in December) is sufficiently vague that I doubt anybody at Apple could narrow down which of their seeds was leaking.
Believing that Dorsal's December posts indicated a January introduction of the new chip was obviously too optimistic -- the timeline was too short for a new machine introduction. This message is at least consistent with his previous ones in that it implies that the hardware has matured and is in a near-beta state now. This could put it in line with a summer release, either WWDC or MWNY. Not a chance of it happening at Tokyo.
The details of the PCB vs daughtercard design are interesting and new information. I don't know about the impedance stuff, but the high-quality small daughtercard vs lower-quality (but cheaper) main board strikes me as an interesting design innovation. The hope for supporting multiple speeds of DDR is encouraging.
As for why all these rumours might show up at once ... while it might be that they feed off of eachother, it could also be that it is driven by a new round of test hardware from Apple. Dorsal's info tends to be more detailed and insightful, and thus takes longer to come up with ... unlike somebody who reports what he sees at first glance.
<strong>a prototype is one thing, while the shipping product is another.</strong><hr></blockquote>
Amen to that...
Also:
1) Wasn't there a rumor going around that Apple would call the 7500 the G5 even though it's really just a G4 with some G5 features? I mean remember that the original G4 was a G3 with an altivec unit on it.
2) One interesting thing about Dorsal's post was the RapidIO running @ 500MHz. To my knowlegde, the HyperTransport consortium has only gone public with speeds up to 400 MHz. Apple is one of it's strongest players though, and I wouldn't be supprised if they had internal tests going on with higher speed RapidIO.
3) I may have heard wrong, but when your memory goes at 333MHz or 400MHz that L3 cache is really not needed.
Obviously Apple doesn't smack down this shit anymore. First of all, we have all those people who want to look so wise be showing they can't be fooled. Then, if Apple did lay the smack down on some NDA-violator, it would prove that they were telling the truth, and stir up all kinds of publicity about it. That kind of defeats the purpose of all the secrecy, doesn't it?
Naw, Apple would hire a few thugs to smack him down. A chain and a few lead pipes do wonders for information leaks, without getting the media involved.
1) Wasn't there a rumor going around that Apple would call the 7500 the G5 even though it's really just a G4 with some G5 features? I mean remember that the original G4 was a G3 with an altivec unit on it.</strong>
The original Motorola roadmap had the G5 as a 7500 processor. It's only last Fall that Moto changed the roadmap to the current and confusing one. Previsouly, Moto's embedded processors had numbers of 8xxx and G4 processors had numbers of 74xx. All that has been shot to hell now. What I'm saying is that the marketing numbers are irrelevant.
<strong>2) One interesting thing about Dorsal's post was the RapidIO running @ 500MHz. To my knowlegde, the HyperTransport consortium has only gone public with speeds up to 400 MHz. Apple is one of it's strongest players though, and I wouldn't be supprised if they had internal tests going on with higher speed RapidIO.</strong>
Both HT and RapidIO have to scale to 1 GHz clock rates to achieve superior bandwidth. The 500 MHz number is logical if not necessary. Considering that RapidIO, the 16 bit wide version, delivers 4 bytes per clock and at 500 MHz only delivers 2 GByte/s, that's barely enough to support main memory. No wonder there is a memory controller on the CPU die.
<strong>3) I may have heard wrong, but when your memory goes at 333MHz or 400MHz that L3 cache is really not needed.</strong>
You heard wrong. Now, cost could be a completely different issue. Ie, L3 cache won't gain you that much for the cost, so it won't be necessary from that standpoint, but main memory technologies won't be catching up to processor performance in the near future and a multi-cache design has its benefits.
Comments
<strong>... In fact, I believe the impedence should be low enough to allow for 4 DIMM slots.</strong><hr></blockquote>
Just curious what you mean by that... Characteristic impedance of the traces? Output impedance of the driver?
Transmission line theory was a long time ago
Any information about Dual Processors?
also, what speed is the G5 at the moment?
(is it still below 1ghz)
***************************************
<strong>anyway what he said sound real. He just give further detail about the size of the mobo and daughter card which need an certain expertise.
but he did not say :
what is the ata bus : ata 66, 100 , 133 or serial ata ?
amount of L2 cache of the 7500 : 256 KByte or 512 KByte ?
Firewire first generation or firewire second generation
USB or USB 2.
What video card did he see in it ...
If you where able Dorsal M to see that rapid I/O and PCI X was implemanted you will be able to answers at these questions (perhaps not the size of the L2 cache)</strong><hr></blockquote>
Remember this was a prototype most probably designed just to test specific bits so its unlikely it has full spec parts like HDDs, graphics cards etc. If they added it all in there any bugs would be much harder to find.
There might be other beta boxes with various ATA controllers, firewire chipsets etc all designed to iron out problems in those features. Then eventually all the parts will be brought together in one box.
I might be wrong, but I'd do it that way.
Here's hoping these things debut at 2Ghz not 1.2.
<strong>
unless he's making an assumption about who made the chips, i believe he's wrong. motorola isn't making the g5 for apple. although the timing seems about right, just not the source of the chip.</strong><hr></blockquote>
Got that feeling myself, the contract with Moto is up this summer, Apple may opt for IBM. Which would be better since IBM makes lots of different CPUs and is a hired gun to manufacture anything that is thrown at them. I think that it is obvious that Moto is concentrating on the embedded market, at least the embedded market that has little in common with G5 chips.
Ty
<strong>Are these for WWDC in May or MWNY in July? I'm guessing July. I hope something like this is announced to ship in July (or August or September or ...). I've got money for one. My Smurf G3/400 is sloooow ripping MP3 and surfing the web under X.</strong><hr></blockquote>
Those are my two biggest probs in X right now...iTunes and every other MP3 app is dog slow. IE is slightly slower on load speed...but the main prob is scrolling. My other main problem is AIM..but I only use that for file trans. Go Adium!
<strong>At least it's a specific report, and not something about having 6 different G5s, all with different motherboards, different types of RAM, different buses, etc. I find this Dorsal report more believable than some others, but still it's not very believable. Doesn't Apple SEAL the prototype hardware that gets seeded? And if not, then aren't there only a few developers that would need hardware access, and thus wouldn't it be easy for Apple to track down Dorsal's identity?</strong><hr></blockquote>
I was wondering that too. But we're assuming Dorsal M is one developer. Maybe its a group (network?) of people who feed one source - a deep throat if you like.
We'll never know, but italways seems his posts are well researched and therefore more beleivable.
Anyways I do believe what he is saying is true as far as internal development goes, but a prototype is one thing, while the shipping product is another.
You'd think Apple would have clamped down on this leak if he was actually describing real prototypes...
Anyway, at least kormac tried a bit harder. Either kormac was from Korea or he spent some time looking for a korean proxy server. And kormac's speculation was a lot more entertaining.
And if you scrutinize some parts of e-www.motorola.com, it's not hard to figure out why one would believe in the existence of an MPC7500.
<strong>At least it's a specific report, and not something about having 6 different G5s, all with different motherboards, different types of RAM, different buses, etc. I find this Dorsal report more believable than some others, but still it's not very believable. Doesn't Apple SEAL the prototype hardware that gets seeded? And if not, then aren't there only a few developers that would need hardware access, and thus wouldn't it be easy for Apple to track down Dorsal's identity?</strong><hr></blockquote>
Earlier in product development there are generally more wildly varying configurations. As the product develops it narrows down to a more specific design. As it gets closer to the final hardware it becomes more advisable to allow 3rd parties closer access, and thus more knowledge. The above message (and the ones in December) is sufficiently vague that I doubt anybody at Apple could narrow down which of their seeds was leaking.
Believing that Dorsal's December posts indicated a January introduction of the new chip was obviously too optimistic -- the timeline was too short for a new machine introduction. This message is at least consistent with his previous ones in that it implies that the hardware has matured and is in a near-beta state now. This could put it in line with a summer release, either WWDC or MWNY. Not a chance of it happening at Tokyo.
The details of the PCB vs daughtercard design are interesting and new information. I don't know about the impedance stuff, but the high-quality small daughtercard vs lower-quality (but cheaper) main board strikes me as an interesting design innovation. The hope for supporting multiple speeds of DDR is encouraging.
As for why all these rumours might show up at once ... while it might be that they feed off of eachother, it could also be that it is driven by a new round of test hardware from Apple. Dorsal's info tends to be more detailed and insightful, and thus takes longer to come up with ... unlike somebody who reports what he sees at first glance.
the 8500 is the embedded version of the g5.
if you go back and look at THE REGISTER it plainly says that the g5 WAS the 7500 but was renamed the 8500.
from what i understand the 7500 is capable of having "multiple cores and altivec units",up to 4
on a chip.
regardless of whether the 7500 is the "true" g5 or not it will "kill" the appollo chip.
i hope this is the 7500 chip we have been reading about.
i just hope apple puts in all the goodies weve been reading about like usb2.0,gigawire,and the optical port.
this 7500 chip is a 32/64 bit chip which is why 10.2 will be 64-bit.
im very excited indeed.
just imagine running itunes,iphoto or idvd with this machine,it will scream!
<strong>a prototype is one thing, while the shipping product is another.</strong><hr></blockquote>
Amen to that...
Also:
1) Wasn't there a rumor going around that Apple would call the 7500 the G5 even though it's really just a G4 with some G5 features? I mean remember that the original G4 was a G3 with an altivec unit on it.
2) One interesting thing about Dorsal's post was the RapidIO running @ 500MHz. To my knowlegde, the HyperTransport consortium has only gone public with speeds up to 400 MHz. Apple is one of it's strongest players though, and I wouldn't be supprised if they had internal tests going on with higher speed RapidIO.
3) I may have heard wrong, but when your memory goes at 333MHz or 400MHz that L3 cache is really not needed.
<img src="graemlins/smokin.gif" border="0" alt="[Chilling]" />
1) Wasn't there a rumor going around that Apple would call the 7500 the G5 even though it's really just a G4 with some G5 features? I mean remember that the original G4 was a G3 with an altivec unit on it.</strong>
The original Motorola roadmap had the G5 as a 7500 processor. It's only last Fall that Moto changed the roadmap to the current and confusing one. Previsouly, Moto's embedded processors had numbers of 8xxx and G4 processors had numbers of 74xx. All that has been shot to hell now. What I'm saying is that the marketing numbers are irrelevant.
<strong>2) One interesting thing about Dorsal's post was the RapidIO running @ 500MHz. To my knowlegde, the HyperTransport consortium has only gone public with speeds up to 400 MHz. Apple is one of it's strongest players though, and I wouldn't be supprised if they had internal tests going on with higher speed RapidIO.</strong>
Both HT and RapidIO have to scale to 1 GHz clock rates to achieve superior bandwidth. The 500 MHz number is logical if not necessary. Considering that RapidIO, the 16 bit wide version, delivers 4 bytes per clock and at 500 MHz only delivers 2 GByte/s, that's barely enough to support main memory. No wonder there is a memory controller on the CPU die.
<strong>3) I may have heard wrong, but when your memory goes at 333MHz or 400MHz that L3 cache is really not needed.</strong>
You heard wrong. Now, cost could be a completely different issue. Ie, L3 cache won't gain you that much for the cost, so it won't be necessary from that standpoint, but main memory technologies won't be catching up to processor performance in the near future and a multi-cache design has its benefits.