What I didn't write into that post was the that I figure that at the rate intel seems to be going (it seems like there is no stoping them) they will be making 2.4 to 2.6GHz processors by MWNY, or shortly there after. I put 1.8GHz up there because that is what I think they should shoot for. Any thing less is going to put us in the same boat we are in now. It's not what anyone wants to hear, but it's on my mind every time I see that intel commercial.
<img src="graemlins/smokin.gif" border="0" alt="[Chilling]" /> the main consideration for the g5 powermacs that will be introduced in ny will be the motherboard.
from what ive been reading at various sites what they have so far is a hybrid-type motherboard,not a true next generation,all new g5 board.
like i said:i expect to see an all-new powermac motherboard at macworld sf in 2003.
this business about integrating ddr-ram with rapid i/o and L2/L3 cache is tricky business,anyone can drop a new chip into an old motherboard.
as we all know the powermacs have bottlenecks galore and address these issues will take some engineering prowess to say the least.
to be honest with you all,i think its much better to use slower processors,but multiple processors instead of using a fast cpu with a slow bus.
keeping these cpus fed with data is going to be a tough task even with ddr-ram and rapid i/o.
<strong>I don't know where this 800 or 866MHz figure comes from, but I have not mentioned it. The 7500 has a 10 stage pipeline (main) and a pipeline of undetermined length for the FPU units. It apears to be made on a 130nm process (given the amount of die surface area in relation to the on die cache and memory controller) so 866MHz would be a very low balled estimate. The processor speed is based on a ratio of the RapidIO bus; in this case 500MHz * 3, or 1.5GHz. The minimum ratio is 2:1 therefore on a 500MHz system bus you will at the minimum acheive 1.0GHz. The memory controller operates externally with memory at a fixed rate, either 133MHz (266MHz DDR) or 166MHz (333MHz DDR) and is asyncronous with the RapidIO main bus. Internally with the CPU core it is a 256bit wide bus similar to one used by IBM called CoreConnect and operates on the backside of the bus at a fixed ratio speed.</strong><hr></blockquote>
Wow, Dorsal has almost doubled his posts in this one thread alone. We're going to stop paying any attention if you keep this up.
What I really want to know, however, is whether there is any improvement in per-cycle performance relative to the 7455? A new memory bus is great, a 400 MHz gain is great, but if they have extended the pipeline to get there is performance improving or suffering as a result?
I think the point of my original message was missed: I said that I hope the new processor's RapidIO bus would scale quickly in the future. The current spec Dorsal has given us seems fast enough, in terms of throughput at least, but going forward there could be issues unless the RapidIO implementation can be clocked faster. Consider:
- AGP 8x would consume all the bandwidth.
- Motherboard based graphics chips could easily consume 4-8 GB/sec.
- Multiprocessors probably need to communicate via the RapidIO interface.
- PCI is probably going to cease being the primary system interface and the various motherboard devices will talk RapidIO directly (Ethernet, audio, ATA, FireWire, USB), so their throughputs will need to be in addition to the PCI's capability.
- After reading some of the RapidIO technical documents, it looks like there is 10-50% overhead on all RapidIO transactions. This means that the theoretical 2 GB/sec rate computed earlier in the thread is probably only 1 - 1.5 GB/sec realized (depending on the average transaction size).
Don't get me wrong, this setup is a huge improvement over just the MPX bus w/ PCI/AGP bridge. I think the RapidIO spec has room for growth up to about 8 MB/sec, IIRC. Hopefully the 7500 will be able to support that right away, or be revved to that capability quickly. The last thing we want is to go from a 1 GB/sec bus to a 2 GB/sec bus (albeit with RAM on the processor side now), and be stuck there again, meanwhile the competition is racing ahead. This is particularly relevent when GPUs are considered, since they are more of a bandwidth hog than the main processor.
The whole shared processor memory situation becomes pretty sticky in this model, as well. We might see the much-vaunted PPC MP advantage evaporate if the sharing of data between the processors becomes significantly slower.
I think the main thing is PCB technology has to cath up with the RIO spec. The thicker the board layer the faster it can go but the more expensive motherboards get. Maybe someone will develop an insulation that will allow for 1GHz speeds on RIO. Later RIO can expand to 32 bit or dual RIO 16 bit to double the bandwidth to 16GBps.
<strong>I think the main thing is PCB technology has to cath up with the RIO spec. The thicker the board layer the faster it can go but the more expensive motherboards get. Maybe someone will develop an insulation that will allow for 1GHz speeds on RIO. Later RIO can expand to 32 bit or dual RIO 16 bit to double the bandwidth to 16GBps.</strong><hr></blockquote>
PCB issues not withstanding, if the 7500's RIO and/or memory controller is not scalable then Apple once again cannot move forward without Motorola revving the processor. It would sure be nice if (for once) the processor had some legs in terms of system integration so that Apple didn't need to wait for Moto to give them a new processor to make their systems faster (as opposed to the processors faster, which is clearly solely up to Moto).
The more that is put into the processor, the more it is out of Apple's hands (or perhaps that should be "the more that it is in Moto's hands"). Higher processor integration is better (and is the future), but it has its dark side as well...
I just got through with the G5 and this machine rocks. Unfortunately, there are a lot of bugs and one of my superiors just said to leave the machine and redesign a new chip. One of the main problems is that the DDR 133 doesn't support the keyboard and so the drivebay won't open because of a glitch in the airport card that links the case to the hard drive of the flash card of the BRAND NEW 23" CINEMA DISPLAY. Another bug is that the chip stops working after a couple of controlled power surges (I don't know why). Then the mobo, um, breaks and, um, won't work. So Apple really needs to finish the work on this machine, um, But it really rocks!!!
<strong>[qb]Both HT and RapidIO have to scale to 1 GHz clock rates to achieve superior bandwidth. The 500 MHz number is logical if not necessary. Considering that RapidIO, the 16 bit wide version, delivers 4 bytes per clock and at 500 MHz only delivers 2 GByte/s, that's barely enough to support main memory. No wonder there is a memory controller on the CPU die.
</strong><hr></blockquote>
Not entirely sure about RapidIO but with HyperTransport the protocol allows for full duplex operation meaning that the data can be both sent and received simulataneously allowing for twice the amount of bandwidth you have identified.
Not entirely sure about RapidIO but with HyperTransport the protocol allows for full duplex operation meaning that the data can be both sent and received simulataneously allowing for twice the amount of bandwidth you have identified.</strong>
RapidIO is full duplex as well. Okay, a 500 MHz 16 bit wide RapidIO bus can deliver 2 GByte/s in one direction.
What is really confusing me is that Apple is a member, a founding member, of the HyperTransport Consortium. Why invest the resources when your processor vendor is the main force behind a competing bus architecture, and will use RapidIO in its future processors? Unless Apple convinced Moto to design a PPC processor with a HyperTransport bus, why promote it? And using HT to connect core logic chips seems a waste when RIO is perfectly fine for it.
[quote] - Multiprocessors probably need to communicate via the RapidIO interface. <hr></blockquote>
Don't forget that RIO is a switched bus- this means that any two (unique!) given devices can talk together with full theoretical bandwidth between them. So, for example, if the HDD needs to write to RAM, there's (in this 500 MHz 16-bit RIO example) 2 GB/s for it to do so, while at the same time, there's 2 GB/s for (say) two CPUs to talk to each other.
Think switch instead of hub, to borrow a networking analogy.
As for future scaling, although I could be wrong, I really don't see this as a problem for RIO. One of the benefits of reducing pin count by moving to a "narrower" bus (16 bits for RIO instead of 64 for current system busses, a la 60x or MPX) is that it makes it easier to design circuits for reduced crosstalk, leakage, etc.
Although if I wanted to complain, I would argue that Apple's chipsets are Apple's problems, and Apple needs to spend more of that $4x10^9 kitty on designers.
A valid question is, since the PMG4 is supposed to Apple's high-end "workstation-class" computer, why is it only using a 64-bit bus? MPX allows for 128. Also, why hasn't, say, a 128-bit bus between northbridge and CPU been implemented, and dual 64-bit busses out to RAM (from the northbridge) been implemented to effectively interleave?
In other words, a lot of Apple's performance problems can be laid squarely at the feet of Apple instead of Moto.
The G4 itself can only handle 64bit MPX. It's the same argument as why Apple cannot use DDR memory; the bus does not support it. MPX specs theoretically support 128 bit MPX... but none of Motorolas parts do. The pin count would have to be very large.
Another brain teaser; why doesn't motorolas own memory controller (the MPC107) support MPX on the G4? It's only able to use the 60X bus. It's sad really.
Don't forget that RIO is a switched bus- this means that any two (unique!) given devices can talk together with full theoretical bandwidth between them. So, for example, if the HDD needs to write to RAM, there's (in this 500 MHz 16-bit RIO example) 2 GB/s for it to do so, while at the same time, there's 2 GB/s for (say) two CPUs to talk to each other.
This case is only possible if CPU has two implemented RapidIo switches.
866MHz G5?? Gawd I hope not! It better be at least 1.2 GHz!!</strong><hr></blockquote>
I wouldn't worry about the validity of this screen shot. If by some odd chance you think this might be real (http://homepage.ntlworld.com/phillip.briggs1/G5_3.htm), I suggest you check out the other pages on this web site that were not part of the original link:
<strong>What I didn't write into that post was the that I figure that at the rate intel seems to be going (it seems like there is no stoping them) they will be making 2.4 to 2.6GHz processors by MWNY, or shortly there after. I put 1.8GHz up there because that is what I think they should shoot for. Any thing less is going to put us in the same boat we are in now. It's not what anyone wants to hear, but it's on my mind every time I see that intel commercial.</strong><hr></blockquote>
I understand what you're saying, but it's really still a bit premature to worry about clock speed before we know anything substantial about the G5 design. For example, if the rumored SPEC performance (as reported by the Register), is correct or even ball park (which I'd be surprised if it was), it would take a 4 GHZ P4 to even start to approach a 1.6 GHZ G5. That said, worrying about MHZ at this stage is sort of like worrying about how many RPMs your next car will do before you've even decided to stick with the old 4cyl. engine or go with a new 8 cyl. engine. MHZ (like RPM) is a very relative measure of performance.
I understand what you're saying, but it's really still a bit premature to worry about clock speed before we know anything substantial about the G5 design. For example, if the rumored SPEC performance (as reported by the Register), is correct or even ball park (which I'd be surprised if it was), it would take a 4 GHZ P4 to even start to approach a 1.6 GHZ G5. That said, worrying about MHZ at this stage is sort of like worrying about how many RPMs your next car will do before you've even decided to stick with the old 4cyl. engine or go with a new 8 cyl. engine. MHZ (like RPM) is a very relative measure of performance.
Steve</strong><hr></blockquote>
RPM fits in but you must add the torque factor. The 125 cc KTM can run up to 14,000 rpm with 60 HP and the KTM 500 has 50 HP but the 125 will never catch the 500 pulling up a hill.
Comments
from what ive been reading at various sites what they have so far is a hybrid-type motherboard,not a true next generation,all new g5 board.
like i said:i expect to see an all-new powermac motherboard at macworld sf in 2003.
this business about integrating ddr-ram with rapid i/o and L2/L3 cache is tricky business,anyone can drop a new chip into an old motherboard.
as we all know the powermacs have bottlenecks galore and address these issues will take some engineering prowess to say the least.
to be honest with you all,i think its much better to use slower processors,but multiple processors instead of using a fast cpu with a slow bus.
keeping these cpus fed with data is going to be a tough task even with ddr-ram and rapid i/o.
<strong>yeah, what about the case design other than the fact that the designers worked hard on it? spill it buddy....</strong><hr></blockquote>
I no longer work at Apple so I am allowed to guess
Look at the new 23" Display... <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />
various sites what they have so far is a hybrid-type motherboard,not a
true next generation,all new g5 board.</strong><hr></blockquote>
... yes, but those "sites" don't know any better than we do, do they?
<strong>I don't know where this 800 or 866MHz figure comes from, but I have not mentioned it. The 7500 has a 10 stage pipeline (main) and a pipeline of undetermined length for the FPU units. It apears to be made on a 130nm process (given the amount of die surface area in relation to the on die cache and memory controller) so 866MHz would be a very low balled estimate. The processor speed is based on a ratio of the RapidIO bus; in this case 500MHz * 3, or 1.5GHz. The minimum ratio is 2:1 therefore on a 500MHz system bus you will at the minimum acheive 1.0GHz. The memory controller operates externally with memory at a fixed rate, either 133MHz (266MHz DDR) or 166MHz (333MHz DDR) and is asyncronous with the RapidIO main bus. Internally with the CPU core it is a 256bit wide bus similar to one used by IBM called CoreConnect and operates on the backside of the bus at a fixed ratio speed.</strong><hr></blockquote>
Wow, Dorsal has almost doubled his posts in this one thread alone. We're going to stop paying any attention if you keep this up.
What I really want to know, however, is whether there is any improvement in per-cycle performance relative to the 7455? A new memory bus is great, a 400 MHz gain is great, but if they have extended the pipeline to get there is performance improving or suffering as a result?
<strong>
* bandwidth is not transferrate
* there's only one PCI bus with 4 Slots
* a PowerMac has 2 USB busses
- 1GB/s AGP 4x
- 266MB/s 64-bit/33MHz PCI
- 100MB/s Firewire2
- 120MB/s USB 2
Total = 1.5 GB/s</strong><hr></blockquote>
I think the point of my original message was missed: I said that I hope the new processor's RapidIO bus would scale quickly in the future. The current spec Dorsal has given us seems fast enough, in terms of throughput at least, but going forward there could be issues unless the RapidIO implementation can be clocked faster. Consider:
- AGP 8x would consume all the bandwidth.
- Motherboard based graphics chips could easily consume 4-8 GB/sec.
- Multiprocessors probably need to communicate via the RapidIO interface.
- PCI is probably going to cease being the primary system interface and the various motherboard devices will talk RapidIO directly (Ethernet, audio, ATA, FireWire, USB), so their throughputs will need to be in addition to the PCI's capability.
- After reading some of the RapidIO technical documents, it looks like there is 10-50% overhead on all RapidIO transactions. This means that the theoretical 2 GB/sec rate computed earlier in the thread is probably only 1 - 1.5 GB/sec realized (depending on the average transaction size).
Don't get me wrong, this setup is a huge improvement over just the MPX bus w/ PCI/AGP bridge. I think the RapidIO spec has room for growth up to about 8 MB/sec, IIRC. Hopefully the 7500 will be able to support that right away, or be revved to that capability quickly. The last thing we want is to go from a 1 GB/sec bus to a 2 GB/sec bus (albeit with RAM on the processor side now), and be stuck there again, meanwhile the competition is racing ahead. This is particularly relevent when GPUs are considered, since they are more of a bandwidth hog than the main processor.
The whole shared processor memory situation becomes pretty sticky in this model, as well. We might see the much-vaunted PPC MP advantage evaporate if the sharing of data between the processors becomes significantly slower.
[ 03-22-2002: Message edited by: Programmer ]</p>
<strong>I think the main thing is PCB technology has to cath up with the RIO spec. The thicker the board layer the faster it can go but the more expensive motherboards get. Maybe someone will develop an insulation that will allow for 1GHz speeds on RIO. Later RIO can expand to 32 bit or dual RIO 16 bit to double the bandwidth to 16GBps.</strong><hr></blockquote>
PCB issues not withstanding, if the 7500's RIO and/or memory controller is not scalable then Apple once again cannot move forward without Motorola revving the processor. It would sure be nice if (for once) the processor had some legs in terms of system integration so that Apple didn't need to wait for Moto to give them a new processor to make their systems faster (as opposed to the processors faster, which is clearly solely up to Moto).
The more that is put into the processor, the more it is out of Apple's hands (or perhaps that should be "the more that it is in Moto's hands"). Higher processor integration is better (and is the future), but it has its dark side as well...
[ 03-22-2002: Message edited by: DOSAL ]</p>
<strong>[qb]Both HT and RapidIO have to scale to 1 GHz clock rates to achieve superior bandwidth. The 500 MHz number is logical if not necessary. Considering that RapidIO, the 16 bit wide version, delivers 4 bytes per clock and at 500 MHz only delivers 2 GByte/s, that's barely enough to support main memory. No wonder there is a memory controller on the CPU die.
</strong><hr></blockquote>
Not entirely sure about RapidIO but with HyperTransport the protocol allows for full duplex operation meaning that the data can be both sent and received simulataneously allowing for twice the amount of bandwidth you have identified.
Not entirely sure about RapidIO but with HyperTransport the protocol allows for full duplex operation meaning that the data can be both sent and received simulataneously allowing for twice the amount of bandwidth you have identified.</strong>
RapidIO is full duplex as well. Okay, a 500 MHz 16 bit wide RapidIO bus can deliver 2 GByte/s in one direction.
What is really confusing me is that Apple is a member, a founding member, of the HyperTransport Consortium. Why invest the resources when your processor vendor is the main force behind a competing bus architecture, and will use RapidIO in its future processors? Unless Apple convinced Moto to design a PPC processor with a HyperTransport bus, why promote it? And using HT to connect core logic chips seems a waste when RIO is perfectly fine for it.
Don't forget that RIO is a switched bus- this means that any two (unique!) given devices can talk together with full theoretical bandwidth between them. So, for example, if the HDD needs to write to RAM, there's (in this 500 MHz 16-bit RIO example) 2 GB/s for it to do so, while at the same time, there's 2 GB/s for (say) two CPUs to talk to each other.
Think switch instead of hub, to borrow a networking analogy.
As for future scaling, although I could be wrong, I really don't see this as a problem for RIO. One of the benefits of reducing pin count by moving to a "narrower" bus (16 bits for RIO instead of 64 for current system busses, a la 60x or MPX) is that it makes it easier to design circuits for reduced crosstalk, leakage, etc.
Although if I wanted to complain, I would argue that Apple's chipsets are Apple's problems, and Apple needs to spend more of that $4x10^9 kitty on designers.
A valid question is, since the PMG4 is supposed to Apple's high-end "workstation-class" computer, why is it only using a 64-bit bus? MPX allows for 128. Also, why hasn't, say, a 128-bit bus between northbridge and CPU been implemented, and dual 64-bit busses out to RAM (from the northbridge) been implemented to effectively interleave?
In other words, a lot of Apple's performance problems can be laid squarely at the feet of Apple instead of Moto.
-HOS
Another brain teaser; why doesn't motorolas own memory controller (the MPC107) support MPX on the G4? It's only able to use the 60X bus. It's sad really.
Blame: shifted back to Motorola.
[QB]
Don't forget that RIO is a switched bus- this means that any two (unique!) given devices can talk together with full theoretical bandwidth between them. So, for example, if the HDD needs to write to RAM, there's (in this 500 MHz 16-bit RIO example) 2 GB/s for it to do so, while at the same time, there's 2 GB/s for (say) two CPUs to talk to each other.
This case is only possible if CPU has two implemented RapidIo switches.
Rooster
<strong>
866MHz G5?? Gawd I hope not! It better be at least 1.2 GHz!!</strong><hr></blockquote>
I wouldn't worry about the validity of this screen shot. If by some odd chance you think this might be real (http://homepage.ntlworld.com/phillip.briggs1/G5_3.htm), I suggest you check out the other pages on this web site that were not part of the original link:
<a href="http://homepage.ntlworld.com/phillip.briggs1/G5_1.htm"; target="_blank">http://homepage.ntlworld.com/phillip.briggs1/G5_1.htm</a>;
<a href="http://homepage.ntlworld.com/phillip.briggs1/G5_2.htm"; target="_blank">http://homepage.ntlworld.com/phillip.briggs1/G5_2.htm</a>;
<strong>What I didn't write into that post was the that I figure that at the rate intel seems to be going (it seems like there is no stoping them) they will be making 2.4 to 2.6GHz processors by MWNY, or shortly there after. I put 1.8GHz up there because that is what I think they should shoot for. Any thing less is going to put us in the same boat we are in now. It's not what anyone wants to hear, but it's on my mind every time I see that intel commercial.</strong><hr></blockquote>
I understand what you're saying, but it's really still a bit premature to worry about clock speed before we know anything substantial about the G5 design. For example, if the rumored SPEC performance (as reported by the Register), is correct or even ball park (which I'd be surprised if it was), it would take a 4 GHZ P4 to even start to approach a 1.6 GHZ G5. That said, worrying about MHZ at this stage is sort of like worrying about how many RPMs your next car will do before you've even decided to stick with the old 4cyl. engine or go with a new 8 cyl. engine. MHZ (like RPM) is a very relative measure of performance.
Steve
<strong>
I understand what you're saying, but it's really still a bit premature to worry about clock speed before we know anything substantial about the G5 design. For example, if the rumored SPEC performance (as reported by the Register), is correct or even ball park (which I'd be surprised if it was), it would take a 4 GHZ P4 to even start to approach a 1.6 GHZ G5. That said, worrying about MHZ at this stage is sort of like worrying about how many RPMs your next car will do before you've even decided to stick with the old 4cyl. engine or go with a new 8 cyl. engine. MHZ (like RPM) is a very relative measure of performance.
Steve</strong><hr></blockquote>
RPM fits in but you must add the torque factor. The 125 cc KTM can run up to 14,000 rpm with 60 HP and the KTM 500 has 50 HP but the 125 will never catch the 500 pulling up a hill.