Anyway, at least kormac tried a bit harder. Either kormac was from Korea or he spent some time looking for a korean proxy server. And kormac's speculation was a lot more entertaining.
And if you scrutinize some parts of e-www.motorola.com, it's not hard to figure out why one would believe in the existence of an MPC7500.</strong><hr></blockquote>
Ah the glory of obfuscated opinions. Nice on Eugene! It took me 2 looks at it before it hit home.
BTS Optimization/ATP CDMA LMF Software Release 15. X SC 611 1.9 GHz and 800 MHz CDMA English Sep 2000 68P64114A84?3 FOA Notice While reasonable efforts have been made to assure the accuracy of this ...
BTS Optimization/ATP CDMA LMF Software Release 15. X SC 611 1.9 GHz and 800 MHz CDMA English Sep 2000 68P64114A84?3 FOA Notice While reasonable efforts have been made to assure the accuracy of this ...
I do now after fishing around on mot's site some more... What was I thinking (I guess we all want a 1.9Ghz G5...) <img src="graemlins/embarrassed.gif" border="0" alt="[Embarrassed]" />
They share a couple of similarities... but so would any advanced chip, especially one designed by the same company!
My biggest concern about these specs (if true) is that the AGP/PCI bus would be across the RapidIO bus which, as pointed out by THT, tops out at around 2 GBytes/sec in the specified configuration. That could be a bit limiting if the I/O system is doing memory operations across the RapidIO bus (which it has to do now since the memory controller is on the chip). Hopefully the RapidIO bus on this chip can be scaled quickly to higher rates. Still, it would be a big step up from the current systems.
[quote] ...AGP/PCI bus would be across the RapidIO bus... <hr></blockquote>
Let's do a real quick thought experiment.
Assume that the CPU and RAM are on a daughterboard, and the AGP/PCI busses are all on the motherboard.
In current designs (CPU on daughterboard, RAM on motherboard), there's one big bus which connects the CPU to the RAM to the AGP/PCI, which is shared amongst them.
In the design above (RAM on daughterboard), now our one big bus only has to connect daughterboard to AGP/PCI (plus secondary busses like IDE/Firewire/USB, etc).
So in current designs, our bandwidth is shared, with lots of chances for contention, where one device (say RAM) needs the bus a lot more often than other devices (say Firewire).
But in the newer design, without the RAM causing bus contention, the bus bandwidth doesn't need to be as big- since CPU-to-RAM communication is off of it!
Further, with this in mind, what's the max bandwidth of 4x AGP? 1 GB/s. What's the max bandwidth of PCI? 133 MB/s. What's the max bandwidth of Firewire? 50 MB/s. In other words, all these secondary devices are less than the 2 GB/s offered by a 500 MHz 16-bit bus.
What will be interesting is, what's the bandwidth between CPU and DDR RAM? Will Apple opt for a Workstation-class 128-bit DDR bus, or will they go industry-standard 64? What about implementing multiple channels of DDR RAM (assuming the G5's presumed built-in DDR controller supports it), the way Via/Intel etc. are going?
The max bandwidth of the PCI of the powermac G4 on 133 mhz mobo is 215 MB/s, it's 64 bit bus PCI.
Anyway your thoughts are very interesting, the existence of two bus : one especially for the ram and the others for PCI bus, and others, can bring overall performance to the system.
If the 2 GB/s bandwidth is fully use, it will make a big difference with a 2 GB/s bandwidth from the PC world.
<strong>LOTS OF INTERESTING STUFF</strong><hr></blockquote>(but I won't waste form space; scroll up if you want to see it)
Thanks for the info I'm not as knowledgeable on this stuff as I used to be (obviously) <img src="graemlins/embarrassed.gif" border="0" alt="[Embarrassed]" />
One more thing (since you seem to know a lot about HT) it's busses can go beyond 16 bit, right?
<strong>In current designs (CPU on daughterboard, RAM on motherboard), there's one big bus which connects the CPU to the RAM to the AGP/PCI, which is shared amongst them.
In the design above (RAM on daughterboard), now our one big bus only has to connect daughterboard to AGP/PCI (plus secondary busses like IDE/Firewire/USB, etc).</strong><hr></blockquote>
I might be mistaken, but I think I just realized why Apple is crowing about DDR-SDRAM L3 cache in the current PowerMacs: in the next motherboard design, main RAM is going to be the L3 cache! It'll be on the daughtercard with its own pipe to the processor.
In other words, the CPU is already there, and the motherboard is catching up!
[edit: This also explains why Apple is taking so long to implement DDR: They're implementing a design that I don't think has occurred to anyone else - certainly not anyone in the personal computer industry.]
I might be mistaken, but I think I just realized why Apple is crowing about DDR-SDRAM L3 cache in the current PowerMacs: in the next motherboard design, main RAM is going to be the L3 cache! It'll be on the daughtercard with its own pipe to the processor.
In other words, the CPU is already there, and the motherboard is catching up!
[edit: This also explains why Apple is taking so long to implement DDR: They're implementing a design that I don't think has occurred to anyone else - certainly not anyone in the personal computer industry.]
I think you are a little too enthousiastic, Amorph, the L3 Cache of the 7455 is limited to 2 MB, very far from what you can have with 3 DDRAM slots.</strong><hr></blockquote>
OK, so maybe the memory controller needs a bump. Still, the architecture is there, it seems to me.
Comments
<strong>
Anyway, at least kormac tried a bit harder. Either kormac was from Korea or he spent some time looking for a korean proxy server. And kormac's speculation was a lot more entertaining.
And if you scrutinize some parts of e-www.motorola.com, it's not hard to figure out why one would believe in the existence of an MPC7500.</strong><hr></blockquote>
Ah the glory of obfuscated opinions. Nice on Eugene! It took me 2 looks at it before it hit home.
:cool:
I did a <a href="http://search.motorola.com/semiconductors/query.html?col=corp&col=sps&col=mcg&charset=iso-8859-1&ht=0&qp=&qt=64bit+7500&qs=&qc=&pw=100%&ws=1&la =en&qm=0&st=1&nh=25&lk=1&rf=0&rq=0&si=0" target="_blank">search</a> for 64bit 7500 at motorola's site. Look at the first 2 results,
frontmat
BTS Optimization/ATP CDMA LMF Software Release 15. X SC 611 1.9 GHz and 800 MHz CDMA English Sep 2000 68P64114A84?3 FOA Notice While reasonable efforts have been made to assure the accuracy of this ...
<a href="http://ted.motorola.com/CDMA/documentation/productdoc/FOA/114a84-3.pdf"; target="_blank">http://ted.motorola.com/CDMA/documentation/productdoc/FOA/114a84-3.pdf</a>; - 7790.2KB - 7500: 4
binder
1.9 GHz and 800 MHz CDMA 68P64114A43?O BTS Optimization/ATP SC 611 TECHNICAL EDUCATION & DOCUMENTATION PREMIER GLOBAL INFORMATION PROVIDER CDMA LMF Software Release 2.8.x and 2. ...
<a href="http://ted.motorola.com/CDMA/documentation/productdoc/GA/114a43-o.pdf"; target="_blank">http://ted.motorola.com/CDMA/documentation/productdoc/GA/114a43-o.pdf</a>; - 2038.8KB - 7500: 4
They are password protected so I was not able to access them...
Actually I think that this has something to do with their cell phones... <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />
I might be wrong though.
[ 03-20-2002: Message edited by: imacman287 ]</p>
<strong>This is interesting....
I did a <a href="http://search.motorola.com/semiconductors/query.html?col=corp&col=sps&col=mcg&charset=iso-8859-1&ht=0&qp=&qt=64bit+7500&qs=&qc=&pw=100%&ws=1&la =en&qm=0&st=1&nh=25&lk=1&rf=0&rq=0&si=0" target="_blank">search</a> for 64bit 7500 at motorola's site. Look at the first 2 results,
frontmat
BTS Optimization/ATP CDMA LMF Software Release 15. X SC 611 1.9 GHz and 800 MHz CDMA English Sep 2000 68P64114A84?3 FOA Notice While reasonable efforts have been made to assure the accuracy of this ...
<a href="http://ted.motorola.com/CDMA/documentation/productdoc/FOA/114a84-3.pdf"; target="_blank">http://ted.motorola.com/CDMA/documentation/productdoc/FOA/114a84-3.pdf</a>; - 7790.2KB - 7500: 4
binder
1.9 GHz and 800 MHz CDMA 68P64114A43?O BTS Optimization/ATP SC 611 TECHNICAL EDUCATION & DOCUMENTATION PREMIER GLOBAL INFORMATION PROVIDER CDMA LMF Software Release 2.8.x and 2. ...
<a href="http://ted.motorola.com/CDMA/documentation/productdoc/GA/114a43-o.pdf"; target="_blank">http://ted.motorola.com/CDMA/documentation/productdoc/GA/114a43-o.pdf</a>; - 2038.8KB - 7500: 4
They are password protected so I was not able to access them...
Actually I think that this has something to do with their cell phones... <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />
I might be wrong though.
[ 03-20-2002: Message edited by: imacman287 ]</strong><hr></blockquote>
You do realize that 1.9GHz and 800Mhz are not chip speeds, but the frequencies that cell phones operate at?
<strong>Dorsal's specs look like <a href="http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=02M0ylfVS0lM9 43030450467M98655" target="_blank">this.</a></strong><hr></blockquote>
They share a couple of similarities... but so would any advanced chip, especially one designed by the same company!
My biggest concern about these specs (if true) is that the AGP/PCI bus would be across the RapidIO bus which, as pointed out by THT, tops out at around 2 GBytes/sec in the specified configuration. That could be a bit limiting if the I/O system is doing memory operations across the RapidIO bus (which it has to do now since the memory controller is on the chip). Hopefully the RapidIO bus on this chip can be scaled quickly to higher rates. Still, it would be a big step up from the current systems.
Let's do a real quick thought experiment.
Assume that the CPU and RAM are on a daughterboard, and the AGP/PCI busses are all on the motherboard.
In current designs (CPU on daughterboard, RAM on motherboard), there's one big bus which connects the CPU to the RAM to the AGP/PCI, which is shared amongst them.
In the design above (RAM on daughterboard), now our one big bus only has to connect daughterboard to AGP/PCI (plus secondary busses like IDE/Firewire/USB, etc).
So in current designs, our bandwidth is shared, with lots of chances for contention, where one device (say RAM) needs the bus a lot more often than other devices (say Firewire).
But in the newer design, without the RAM causing bus contention, the bus bandwidth doesn't need to be as big- since CPU-to-RAM communication is off of it!
Further, with this in mind, what's the max bandwidth of 4x AGP? 1 GB/s. What's the max bandwidth of PCI? 133 MB/s. What's the max bandwidth of Firewire? 50 MB/s. In other words, all these secondary devices are less than the 2 GB/s offered by a 500 MHz 16-bit bus.
What will be interesting is, what's the bandwidth between CPU and DDR RAM? Will Apple opt for a Workstation-class 128-bit DDR bus, or will they go industry-standard 64? What about implementing multiple channels of DDR RAM (assuming the G5's presumed built-in DDR controller supports it), the way Via/Intel etc. are going?
Just a few thoughts,
-HOS
<strong>
What's the max bandwidth of PCI? 133 MB/s.
-HOS</strong><hr></blockquote>
The max bandwidth of the PCI of the powermac G4 on 133 mhz mobo is 215 MB/s, it's 64 bit bus PCI.
Anyway your thoughts are very interesting, the existence of two bus : one especially for the ram and the others for PCI bus, and others, can bring overall performance to the system.
If the 2 GB/s bandwidth is fully use, it will make a big difference with a 2 GB/s bandwidth from the PC world.
max bandwidth for firewire2 is 800Mb/s
i think...actually am pretty sure.
Peace,
G
<strong>the max bandwidth for firewire is 400Mb/s
max bandwidth for firewire2 is 800Mb/s
i think...actually am pretty sure.
Peace,
G</strong><hr></blockquote>
Firewire2 (aka 1394b) starts at 800Mbps and goes up to 3.2Gbps depending on the cable type (copper, plastic optical, glass optical fiber).
<strong>the max bandwidth for firewire is 400Mb/s
max bandwidth for firewire2 is 800Mb/s</strong><hr></blockquote>
You do know the difference between a bit and a byte, don't you? 800Mb/s is only 100MB/s.
What you might need at maximum:
- 1GB/s AGP
- 4*215GB/s 64-bit PCI = 860MB/s
- 100MB/s Firewire2
- 60MB/s USB 2
Total = 2020MB/s
Assuming that you will probably never max out everything at the same time, RapidIO seems good enough to me. I'm not going to wait for the G6
<strong>LOTS OF INTERESTING STUFF</strong><hr></blockquote>(but I won't waste form space; scroll up if you want to see it)
Thanks for the info
One more thing (since you seem to know a lot about HT) it's busses can go beyond 16 bit, right?
<strong>Dorsal's specs look like <a href="http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=02M0ylfVS0lM9 43030450467M98655" target="_blank">this.</a></strong><hr></blockquote>
And why should't they? <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />
<strong>What you might need at maximum:
- 1GB/s AGP
- 4*215GB/s 64-bit PCI = 860MB/s
- 100MB/s Firewire2
- 60MB/s USB 2
Total = 2020MB/s
</strong><hr></blockquote>
* bandwidth is not transferrate
* there's only one PCI bus with 4 Slots
* a PowerMac has 2 USB busses
- 1GB/s AGP 4x
- 266MB/s 64-bit/33MHz PCI
- 100MB/s Firewire2
- 120MB/s USB 2
Total = 1.5 GB/s
Peace,
G
we like bold letters haha
<strong>In current designs (CPU on daughterboard, RAM on motherboard), there's one big bus which connects the CPU to the RAM to the AGP/PCI, which is shared amongst them.
In the design above (RAM on daughterboard), now our one big bus only has to connect daughterboard to AGP/PCI (plus secondary busses like IDE/Firewire/USB, etc).</strong><hr></blockquote>
I might be mistaken, but I think I just realized why Apple is crowing about DDR-SDRAM L3 cache in the current PowerMacs: in the next motherboard design, main RAM is going to be the L3 cache! It'll be on the daughtercard with its own pipe to the processor.
In other words, the CPU is already there, and the motherboard is catching up!
[edit: This also explains why Apple is taking so long to implement DDR: They're implementing a design that I don't think has occurred to anyone else - certainly not anyone in the personal computer industry.]
[ 03-20-2002: Message edited by: Amorph ]</p>
<strong>
I might be mistaken, but I think I just realized why Apple is crowing about DDR-SDRAM L3 cache in the current PowerMacs: in the next motherboard design, main RAM is going to be the L3 cache! It'll be on the daughtercard with its own pipe to the processor.
In other words, the CPU is already there, and the motherboard is catching up!
[edit: This also explains why Apple is taking so long to implement DDR: They're implementing a design that I don't think has occurred to anyone else - certainly not anyone in the personal computer industry.]
[ 03-20-2002: Message edited by: Amorph ]</strong><hr></blockquote>
I think you are a little too enthousiastic, Amorph, the L3 Cache of the 7455 is limited to 2 MB, very far from what you can have with 3 DDRAM slots.
<strong>
I think you are a little too enthousiastic, Amorph, the L3 Cache of the 7455 is limited to 2 MB, very far from what you can have with 3 DDRAM slots.</strong><hr></blockquote>
OK, so maybe the memory controller needs a bump.