Don't forget that RIO is a switched bus- this means that any two (unique!) given devices can talk together with full theoretical bandwidth between them. So, for example, if the HDD needs to write to RAM, there's (in this 500 MHz 16-bit RIO example) 2 GB/s for it to do so, while at the same time, there's 2 GB/s for (say) two CPUs to talk to each other.
Think switch instead of hub, to borrow a networking analogy.
As for future scaling, although I could be wrong, I really don't see this as a problem for RIO. One of the benefits of reducing pin count by moving to a "narrower" bus (16 bits for RIO instead of 64 for current system busses, a la 60x or MPX) is that it makes it easier to design circuits for reduced crosstalk, leakage, etc.
Although if I wanted to complain, I would argue that Apple's chipsets are Apple's problems, and Apple needs to spend more of that $4x10^9 kitty on designers.
A valid question is, since the PMG4 is supposed to Apple's high-end "workstation-class" computer, why is it only using a 64-bit bus? MPX allows for 128. Also, why hasn't, say, a 128-bit bus between northbridge and CPU been implemented, and dual 64-bit busses out to RAM (from the northbridge) been implemented to effectively interleave?
In other words, a lot of Apple's performance problems can be laid squarely at the feet of Apple instead of Moto.
</strong><hr></blockquote>
Apple's $4 billion is needed to supplement their income so they remain profitable. It's also going to cover them through weak quarters, like I expect the next couple to be.
As somebody else supplied: the MPX's theoretical 128-bit width isn't supported by any shipping part.
The RapidIO bus is point to point, but if everybody wants to talk to one point (i.e. the CPU/memory controller/memory) then they all have to share bandwidth. And the 2 GB/sec throughput is theoretical, realized throughput is considerably lower due to packet overhead. Small transactions have a disproportionaly large effect on throughput (i.e. somebody sending 1 byte is almost as expensive as somebody sending 10 bytes).
I wouldn't worry about the validity of this screen shot. If by some odd chance you think this might be real (http://homepage.ntlworld.com/phillip.briggs1/G5_3.htm), I suggest you check out the other pages on this web site that were not part of the original link:
Yeah, I saw those "iMac G5s" earlier...just didn't realize the ASP shot was from the same poster.. <img src="graemlins/embarrassed.gif" border="0" alt="[Embarrassed]" />
You should have realized immediately that it was fake...the carbon ASP (not the one in the term) displays the MHz rounded up, I.E. a 866.66666 on to infinity G5 would appear as 867MHz. Besides you know it's crap anyway .
Well, now that both Dorsal and Kormac have come out of the woodwork, I suppose I should weigh in with my questions as well.
Dorsal, do you note any other capabilities on these machines other than "under-the-hood" improvements (e.g. introduction of new technologies like firewire)? Is there any significant chip-based performance boost (e.g. more altivec units). Or is what you are saying that these things are essentially being built to just do a lot faster what the existing machines already do.
Kormac, good to see you back. I for one noted the intro of the 23 inch display. What are you implying about what might come next? Those links were to pretty boring technologies, not to anything that seemed Apple-like.
<strong> I think the point of my original message was missed</strong><hr></blockquote>
Point taken <img src="graemlins/embarrassed.gif" border="0" alt="[Embarrassed]" />
[quote]Originally posted by Dorsal M:
<strong> The processor speed is based on a ratio of the RapidIO bus; in this case 500MHz * 3, or 1.5GHz. The minimum ratio is 2:1 therefore on a 500MHz system bus you will at the minimum acheive 1.0GHz. </strong><hr></blockquote>
Where did you get that from, I must have missed something in the white papers <img src="confused.gif" border="0">
<strong>I just got through with the G5 and this machine rocks. Unfortunately, there are a lot of bugs and one of my superiors just said to leave the machine and redesign a new chip. One of the main problems is that the DDR 133 doesn't support the keyboard and so the drivebay won't open because of a glitch in the airport card that links the case to the hard drive of the flash card of the BRAND NEW 23" CINEMA DISPLAY. Another bug is that the chip stops working after a couple of controlled power surges (I don't know why). Then the mobo, um, breaks and, um, won't work. So Apple really needs to finish the work on this machine, um, But it really rocks!!!</strong><hr></blockquote>
Funniest thing I've read in long time. I nearly pissed in my pants laughing so hard!!
The only interesting thing about the first link is the 17" PCTV (something that I have always thought that an iMac configuration should has to satisfy consumers w/o a lot of space such a the college market) implying that maybe when the iMac goes 17" that this will be available? <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />
The second article also implies this. But look at this excerpt:
"Many LCD TVs currently on the market still require some technological advancement; for example, their slow pixel response time causes a â??ghostingâ?? problem. However, Samsung Electronics has accomplished some technological breakthroughs."
Now I don't know what this means for the LCD display on a PC... nothing in this article besides that Samsung can make REALLY BIG (40") LCD displays...
<strong>Where did you get that from, I must have missed something in the white papers </strong><hr></blockquote>
It wouldn't be a function of the RapidIO spec, it would be a function of the RapidIO implementation on the processor. If he is who he claims then he could well have access to that sort of processor documentation. It could also be a poor assumption. Or he could be making all this up just to toy with us.
[quote]The RapidIO bus is point to point, but if everybody wants to talk to one point (i.e. the CPU/memory controller/memory) then they all have to share bandwidth. <hr></blockquote>
--Programmer
Yup- point-to-point is why I threw in the "unique!" (implying not shared) line in my post. Sorry it wasn't sufficiently clear.
Anyway, as per the older supposition, the assumption about the G5 is that it will adopt a built-in DDR controller, and thus move from a traditional shared bus approach (as in your CPU/memory controller/memory example above) to one where a CPU's local memory is on a "backside bus", to adopt an older expression.
Thus, in a multiple-CPU situation, each CPU gets its own local memory. However, in order for CPU 1 to access CPU 2's local memory, you use the RapidIO bus to do so.
Pardon the ASCII art:
local DDR RAM <--> CPU 1 <--> RIO bus <--> CPU 2 <--> local DDR RAM
Further, the RIO bus then also provides a way to get to shared subsystems like hard drives, PCI, etc. Again, since this is a switched bus, CPU1 can (say) talk to the hard drive while CPU2 is talking to the AGP card.
It gets really interesting because this approach then assumes you'll need a really big address space- making the jump to 64 bits necessary. Especially as the number of CPUs scale up, assuming 2-3 GB per CPU means we'll get past the 4 GB limit of 2^32 very quickly.
What is really confusing me is that Apple is a member, a founding member, of the HyperTransport Consortium. Why invest the resources when your processor vendor is the main force behind a competing bus architecture, and will use RapidIO in its future processors? Unless Apple convinced Moto to design a PPC processor with a HyperTransport bus, why promote it? And using HT to connect core logic chips seems a waste when RIO is perfectly fine for it.[/QB]<hr></blockquote>
My wild ass conspiracy theory is that Apple intends to leverage Nvidia to make a version of their next integrated core chipset for Apple's machines. Nvidia already uses HyperTransport with AMD's EV6 bus on Nforce motherboards and Intel's GTL+ bus inside the Xbox. Why not go for the triple crown and make a MPX compatible version .
More likely scenario, Apple paid the $40,000 or whatever it costs now to be premier member in the HT consortium for a device/purpose not yet apparent or just for the media exposure. Since Motorola would of course want Apple to use their RapidIO technology I can't imagine them designing the G5 to work with HT.
[quote] My wild ass conspiracy theory is that Apple intends to leverage Nvidia to make a version of their next integrated core chipset for Apple's machines. Nvidia already uses HyperTransport with AMD's EV6 bus on Nforce motherboards and Intel's GTL+ bus inside the Xbox. Why not go for the triple crown and make a MPX compatible version. <hr></blockquote>
You call that a wild ass theory? Pah! I fart in the general direction of your wild ass theory!
OK, here's mine: Apple have a skunkworks project to combine AMD's processors with a PPC-oriented software morphing layer based on Transmeta's technology.
I like this game. Just look up the members of the <a href="http://www.hypertransport.org/organisation"; target="_blank">hypertransport consortium</a>, and conjure up ways that they can combine forces to lead Apple in triumph against the forces of darkness. Do try this at home, kids!
well shit, while we're on wild ass theories, here's mine.
Nvidia is now bored after conquering the GFX market, so they're looking around for some asses to kick.
they've started on chipsets to get their feet wet, and although they aren't at the top yet, they fully expect to hand VIA their collective asses and dominate the chipset market.
so what's next? they decided that Apple is a nice little company that needs a hand, so they decide to make computer processors to go hand in hand with their chipsets and GFX chips. apple's next series of chips will come from Nvidia, and apple will once again be a viable competitor.
My wild ass conspiracy theory is that Apple intends to leverage Nvidia to make a version of their next integrated core chipset for Apple's machines. Nvidia already uses HyperTransport with AMD's EV6 bus on Nforce motherboards and Intel's GTL+ bus inside the Xbox. Why not go for the triple crown and make a MPX compatible version .
More likely scenario, Apple paid the $40,000 or whatever it costs now to be premier member in the HT consortium for a device/purpose not yet apparent or just for the media exposure. Since Motorola would of course want Apple to use their RapidIO technology I can't imagine them designing the G5 to work with HT.</strong><hr></blockquote>
Here is my guess: There are so many new standards out there right now, and it is hard to guess which one will come out on top, Apple is just positioning itself so that whichever one catches on they will be right there. I think that Apple simply doesn't want to get caught in the wrong seat at the end of the song.
Thinking more about it, it would seem that each have there strengths and weaknesses. A daughter card with CPU, Ram, and AGP would be nice. HyperTransport would make the wiring easier, and ensure that the system works well with Nvidia cards. But how about a daughter card that would allow the PCU and Video board to share memory?? I think that Apple really likes the idea of one controller chip, like in the hypertransport protocol.
<strong>Work on the G5 (MPC7500) is progressing nicely at Motorola ...</strong><hr></blockquote>
Very nice.
However, this sure sounds like a rather conservative design.
133 MHz DDR (I really want to be able to go up to 266 MHz [533 MHz equivalent], or, at least, 128 bit) is on the low side (however, as with Motorola's 8500, the memory controller was put on-chip to facilitate rapid increases in memory speed as processor speeds increase).
500 MHz RapidIO is half the speed RapidIO has been capable of for about a year now.
Graphic chips are too far from the CPU currently, and a higher bandwidth connection is required. The level of integration will always increase, and the speed of interconnects will always improve. The graphics engines include advanced memory controllers, so an obvious direction for the graphics companies to move is into the chipset space. If they don't the chipset companies will move into the graphics space and do a louzy job of it. The problem is that the memory controllers are moving onto the CPUs, and the chipsets are being replaced by interconnect strategies like RapidIO. So what is going to happen to the graphics chips? They need to cozy up to the CPU, which means either moving onto the CPU or using a dedicated highspeed interconnect to the CPU's onchip memory controller. Sharing the system interconnect with the rest of the system is insufficient for the graphics engine's ravenous appetite for bandwidth.
Eventually I expect to see processors with onchip memory controllers and 2 bus interfaces -- one to the graphics engine, and one to the rest of the system. The graphics engine may reside on the CPUs chip in highly integrated cases, but for a while (i.e. a few years) they will just be connected by the fastest available point-to-point mechanism. nVidia likes HyperTransport, and I think ATI might jump on that bandwagon too (if they haven't already). Since these buses are designed to be simple and easy to implement, it wouldn't surprise me to see both a RapidIO and a HyperTransport port on future PowerPCs.
The 8540 documentation on the Motorola site talks about a modular approach to designing processors, with customer designed sections. The G5 that Apple eventually uses is likely to follow the same philosophy, even if it is otherwise different than the 8540. This could allow Apple to add a HyperTransport interface for a high speed graphics system, in addition to the standard RapidIO bus that handles all the other interactions with the system.
"Work on the G5 (MPC7500) is progressing nicely at Motorola and I can only assume Apple had a role in the development as there are many features included that are condusive to a top-notch desktop processor capable of bring the PowerMac into the 21st centure as a real performer in the compute intensive field."
one definatly good thing about dorsal posts is that they bring the community together a bit with "inside" info that is posted in a very believable manner, to allow for some good interesting ideas and threads to form.
whether or not dorsal is actually telling leaked info, or if he is just a really good writer with a keen imagination, he's posts usually invoke a strong discussion and out of the discussion good ideas and predictions usually stem
Comments
<strong>
Don't forget that RIO is a switched bus- this means that any two (unique!) given devices can talk together with full theoretical bandwidth between them. So, for example, if the HDD needs to write to RAM, there's (in this 500 MHz 16-bit RIO example) 2 GB/s for it to do so, while at the same time, there's 2 GB/s for (say) two CPUs to talk to each other.
Think switch instead of hub, to borrow a networking analogy.
As for future scaling, although I could be wrong, I really don't see this as a problem for RIO. One of the benefits of reducing pin count by moving to a "narrower" bus (16 bits for RIO instead of 64 for current system busses, a la 60x or MPX) is that it makes it easier to design circuits for reduced crosstalk, leakage, etc.
Although if I wanted to complain, I would argue that Apple's chipsets are Apple's problems, and Apple needs to spend more of that $4x10^9 kitty on designers.
A valid question is, since the PMG4 is supposed to Apple's high-end "workstation-class" computer, why is it only using a 64-bit bus? MPX allows for 128. Also, why hasn't, say, a 128-bit bus between northbridge and CPU been implemented, and dual 64-bit busses out to RAM (from the northbridge) been implemented to effectively interleave?
In other words, a lot of Apple's performance problems can be laid squarely at the feet of Apple instead of Moto.
</strong><hr></blockquote>
Apple's $4 billion is needed to supplement their income so they remain profitable. It's also going to cover them through weak quarters, like I expect the next couple to be.
As somebody else supplied: the MPX's theoretical 128-bit width isn't supported by any shipping part.
The RapidIO bus is point to point, but if everybody wants to talk to one point (i.e. the CPU/memory controller/memory) then they all have to share bandwidth. And the 2 GB/sec throughput is theoretical, realized throughput is considerably lower due to packet overhead. Small transactions have a disproportionaly large effect on throughput (i.e. somebody sending 1 byte is almost as expensive as somebody sending 10 bytes).
<strong>
I wouldn't worry about the validity of this screen shot. If by some odd chance you think this might be real (http://homepage.ntlworld.com/phillip.briggs1/G5_3.htm), I suggest you check out the other pages on this web site that were not part of the original link:
<a href="http://homepage.ntlworld.com/phillip.briggs1/G5_1.htm"; target="_blank">http://homepage.ntlworld.com/phillip.briggs1/G5_1.htm</a>;
<a href="http://homepage.ntlworld.com/phillip.briggs1/G5_2.htm"; target="_blank">http://homepage.ntlworld.com/phillip.briggs1/G5_2.htm</a></strong><hr></blockquote>;
Yeah, I saw those "iMac G5s" earlier...just didn't realize the ASP shot was from the same poster.. <img src="graemlins/embarrassed.gif" border="0" alt="[Embarrassed]" />
Dorsal, do you note any other capabilities on these machines other than "under-the-hood" improvements (e.g. introduction of new technologies like firewire)? Is there any significant chip-based performance boost (e.g. more altivec units). Or is what you are saying that these things are essentially being built to just do a lot faster what the existing machines already do.
Kormac, good to see you back. I for one noted the intro of the 23 inch display. What are you implying about what might come next? Those links were to pretty boring technologies, not to anything that seemed Apple-like.
Hope springs eternal,
Mandricard
AppleOutsider
<strong>
Check your blood pressure Matsu, you're gonna pop a vein.
<strong> I think the point of my original message was missed</strong><hr></blockquote>
Point taken <img src="graemlins/embarrassed.gif" border="0" alt="[Embarrassed]" />
[quote]Originally posted by Dorsal M:
<strong> The processor speed is based on a ratio of the RapidIO bus; in this case 500MHz * 3, or 1.5GHz. The minimum ratio is 2:1 therefore on a 500MHz system bus you will at the minimum acheive 1.0GHz. </strong><hr></blockquote>
Where did you get that from, I must have missed something in the white papers <img src="confused.gif" border="0">
<strong>I just got through with the G5 and this machine rocks. Unfortunately, there are a lot of bugs and one of my superiors just said to leave the machine and redesign a new chip. One of the main problems is that the DDR 133 doesn't support the keyboard and so the drivebay won't open because of a glitch in the airport card that links the case to the hard drive of the flash card of the BRAND NEW 23" CINEMA DISPLAY. Another bug is that the chip stops working after a couple of controlled power surges (I don't know why). Then the mobo, um, breaks and, um, won't work. So Apple really needs to finish the work on this machine, um, But it really rocks!!!</strong><hr></blockquote>
Funniest thing I've read in long time. I nearly pissed in my pants laughing so hard!!
<img src="graemlins/lol.gif" border="0" alt="[Laughing]" />
<strong>
23" Wide UXGA LM230W1
What will be next ?
<a href="http://www.lgphilips-lcd.com:8888/English/news/n_cozy.html?idx=401&offset=0&pkinds=movement&pname =news" target="_blank"> LG Philips LCD</a>
or
<a href="http://www.samsungelectronics.com/semiconductors/TFT_LCD/product_news/semiadmin_1010104542921_108.html"; target="_blank">Samsung LCD</a>
And if you can remember what I was talked about, I think we will see good sign soon.
P.S.: SAMSUNG & LG.Philips LCD Co., Ltd is making TFT-LCD for New iMac.
[ 03-21-2002: Message edited by: kormac77 ]</strong><hr></blockquote>
The only interesting thing about the first link is the 17" PCTV (something that I have always thought that an iMac configuration should has to satisfy consumers w/o a lot of space such a the college market) implying that maybe when the iMac goes 17" that this will be available? <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />
The second article also implies this. But look at this excerpt:
"Many LCD TVs currently on the market still require some technological advancement; for example, their slow pixel response time causes a â??ghostingâ?? problem. However, Samsung Electronics has accomplished some technological breakthroughs."
Now I don't know what this means for the LCD display on a PC... nothing in this article besides that Samsung can make REALLY BIG (40") LCD displays...
[edit: shortened links in quoted text - Amorph]
[ 03-27-2002: Message edited by: Amorph ]</p>
<strong>Where did you get that from, I must have missed something in the white papers
It wouldn't be a function of the RapidIO spec, it would be a function of the RapidIO implementation on the processor. If he is who he claims then he could well have access to that sort of processor documentation. It could also be a poor assumption. Or he could be making all this up just to toy with us.
--Programmer
Yup- point-to-point is why I threw in the "unique!" (implying not shared) line in my post. Sorry it wasn't sufficiently clear.
Anyway, as per the older supposition, the assumption about the G5 is that it will adopt a built-in DDR controller, and thus move from a traditional shared bus approach (as in your CPU/memory controller/memory example above) to one where a CPU's local memory is on a "backside bus", to adopt an older expression.
Thus, in a multiple-CPU situation, each CPU gets its own local memory. However, in order for CPU 1 to access CPU 2's local memory, you use the RapidIO bus to do so.
Pardon the ASCII art:
local DDR RAM <--> CPU 1 <--> RIO bus <--> CPU 2 <--> local DDR RAM
Further, the RIO bus then also provides a way to get to shared subsystems like hard drives, PCI, etc. Again, since this is a switched bus, CPU1 can (say) talk to the hard drive while CPU2 is talking to the AGP card.
It gets really interesting because this approach then assumes you'll need a really big address space- making the jump to 64 bits necessary. Especially as the number of CPUs scale up, assuming 2-3 GB per CPU means we'll get past the 4 GB limit of 2^32 very quickly.
Pretty neat, huh?
-HOS
[QB
What is really confusing me is that Apple is a member, a founding member, of the HyperTransport Consortium. Why invest the resources when your processor vendor is the main force behind a competing bus architecture, and will use RapidIO in its future processors? Unless Apple convinced Moto to design a PPC processor with a HyperTransport bus, why promote it? And using HT to connect core logic chips seems a waste when RIO is perfectly fine for it.[/QB]<hr></blockquote>
My wild ass conspiracy theory is that Apple intends to leverage Nvidia to make a version of their next integrated core chipset for Apple's machines. Nvidia already uses HyperTransport with AMD's EV6 bus on Nforce motherboards and Intel's GTL+ bus inside the Xbox. Why not go for the triple crown and make a MPX compatible version
More likely scenario, Apple paid the $40,000 or whatever it costs now to be premier member in the HT consortium for a device/purpose not yet apparent or just for the media exposure. Since Motorola would of course want Apple to use their RapidIO technology I can't imagine them designing the G5 to work with HT.
[quote] My wild ass conspiracy theory is that Apple intends to leverage Nvidia to make a version of their next integrated core chipset for Apple's machines. Nvidia already uses HyperTransport with AMD's EV6 bus on Nforce motherboards and Intel's GTL+ bus inside the Xbox. Why not go for the triple crown and make a MPX compatible version. <hr></blockquote>
You call that a wild ass theory? Pah! I fart in the general direction of your wild ass theory!
OK, here's mine: Apple have a skunkworks project to combine AMD's processors with a PPC-oriented software morphing layer based on Transmeta's technology.
I like this game. Just look up the members of the <a href="http://www.hypertransport.org/organisation"; target="_blank">hypertransport consortium</a>, and conjure up ways that they can combine forces to lead Apple in triumph against the forces of darkness. Do try this at home, kids!
Nvidia is now bored after conquering the GFX market, so they're looking around for some asses to kick.
they've started on chipsets to get their feet wet, and although they aren't at the top yet, they fully expect to hand VIA their collective asses and dominate the chipset market.
so what's next? they decided that Apple is a nice little company that needs a hand, so they decide to make computer processors to go hand in hand with their chipsets and GFX chips. apple's next series of chips will come from Nvidia, and apple will once again be a viable competitor.
<strong>
My wild ass conspiracy theory is that Apple intends to leverage Nvidia to make a version of their next integrated core chipset for Apple's machines. Nvidia already uses HyperTransport with AMD's EV6 bus on Nforce motherboards and Intel's GTL+ bus inside the Xbox. Why not go for the triple crown and make a MPX compatible version
More likely scenario, Apple paid the $40,000 or whatever it costs now to be premier member in the HT consortium for a device/purpose not yet apparent or just for the media exposure. Since Motorola would of course want Apple to use their RapidIO technology I can't imagine them designing the G5 to work with HT.</strong><hr></blockquote>
Here is my guess: There are so many new standards out there right now, and it is hard to guess which one will come out on top, Apple is just positioning itself so that whichever one catches on they will be right there. I think that Apple simply doesn't want to get caught in the wrong seat at the end of the song.
Thinking more about it, it would seem that each have there strengths and weaknesses. A daughter card with CPU, Ram, and AGP would be nice. HyperTransport would make the wiring easier, and ensure that the system works well with Nvidia cards. But how about a daughter card that would allow the PCU and Video board to share memory?? I think that Apple really likes the idea of one controller chip, like in the hypertransport protocol.
Ty
<strong>Work on the G5 (MPC7500) is progressing nicely at Motorola ...</strong><hr></blockquote>
Very nice.
However, this sure sounds like a rather conservative design.
Graphic chips are too far from the CPU currently, and a higher bandwidth connection is required. The level of integration will always increase, and the speed of interconnects will always improve. The graphics engines include advanced memory controllers, so an obvious direction for the graphics companies to move is into the chipset space. If they don't the chipset companies will move into the graphics space and do a louzy job of it. The problem is that the memory controllers are moving onto the CPUs, and the chipsets are being replaced by interconnect strategies like RapidIO. So what is going to happen to the graphics chips? They need to cozy up to the CPU, which means either moving onto the CPU or using a dedicated highspeed interconnect to the CPU's onchip memory controller. Sharing the system interconnect with the rest of the system is insufficient for the graphics engine's ravenous appetite for bandwidth.
Eventually I expect to see processors with onchip memory controllers and 2 bus interfaces -- one to the graphics engine, and one to the rest of the system. The graphics engine may reside on the CPUs chip in highly integrated cases, but for a while (i.e. a few years) they will just be connected by the fastest available point-to-point mechanism. nVidia likes HyperTransport, and I think ATI might jump on that bandwagon too (if they haven't already). Since these buses are designed to be simple and easy to implement, it wouldn't surprise me to see both a RapidIO and a HyperTransport port on future PowerPCs.
The 8540 documentation on the Motorola site talks about a modular approach to designing processors, with customer designed sections. The G5 that Apple eventually uses is likely to follow the same philosophy, even if it is otherwise different than the 8540. This could allow Apple to add a HyperTransport interface for a high speed graphics system, in addition to the standard RapidIO bus that handles all the other interactions with the system.
I hope you're right masked man.
<img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />
Lemon Bon Bon
whether or not dorsal is actually telling leaked info, or if he is just a really good writer with a keen imagination, he's posts usually invoke a strong discussion and out of the discussion good ideas and predictions usually stem